dess (dess@nospam.com) on 5/21/07 wrote:
---------------------------
>David Kanter (dkanter@realworldtech.com) on 5/21/07 wrote:
>---------------------------
>>In talking with architects, some use the terminology micro-op to refer to what
>>AMD used to call RISCops (Rops), but are most accurately described as internal operations.
>>Some of their documentation refers to macro-ops as the internal operations. I
>>don't really think it matters. I choose the term that makes it easiest for the
>>folks at AMD to edit/revise/comment on my article and >>questions.

>Well, it matters if you use the same term for both AMD's >and Intel's chips, in
>the same context, while it refers to different things. ;)

Unfortunately, I couldn't quite get macro-op, or micro-op to really fit well in the diagrams. We have a 750p wide constraint, and anything larger will cause clipping problems. Hence I prefer uop to micro-op, despite confusion potential. Perhaps I should update the article.

>>However, Intel is a different story. First of all, the >term is uop, not micro-op,
>
>You used "uop" also on Barcelona's diagrams.

See above comments.

>>which refers to the internal operations. In Intel terminology a macro-op is an
>>x86 instruction. So macro-op fusion is the fusing of two x86 instruction (CMP+JMP).
>>
>>>Now I'm confused whether this happened at some places for >the Core 2 as well, or
>>>those are really 4 micro-ops, in which case the Barcelona >is the wider one.
>>
>>Decoding always maps the contents of the Icache (x86 instructions) to the internal
>>operations and operands of the processor in question.
>>
>>AMD has 3 decoders, Intel has 4 decoders. AMD can 3 operations/cycle, Intel can
>>rename 4. Counting execution units is a little tricky since AMD likes to count
>>their separate AGUs as functional units, while Intel considers them part of the
>>memory pipelines. Intel can retire 4 operations, AMD can retire 3.
>>
>>At the end of the day, the Core2 is theoretically wider. However, it's unclear
>>to what extent this will be true in practice.
>>
>>DK
>
>Taking into account that AMD's 3 decoders are responsible >of decoding 95% of the
>instruction set/modes

According to whom, and on what workload?

>(the uCode Engine works with the >remaining 5%,

Again, which workload?

>as one more
>decoder, but it won't work parallel with the other 3), and >emit up to 2 micro-ops
>each, while 3 of Intel's 4 decoders are for more simple >instructions, and so emit
>one uop, Intel's is wider only in case of more simple >instructions are being used.

It seems to me that you probably don't have data on the % of operations that decode to 1,2,3,4+ uops.

>Moreover, AFAIK, AMD's Pack Buffer emits 3 _macro-ops_, >whose can contain up to
>6 micro-ops, while Intel's path is 4 _uop_. Or is this >"uop" a macro-op in AMD's terms?

Intel's uops and AMD's micro-ops, macro-ops, etc. are not really comparable directly. IMHO, the best way to examine the two is statistical analysis...

DK