Richard Cownie (tich@pobox.com) on 8/31/07 wrote:
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>Vincent Diepeveen (diep@xs4all.nl) on 8/31/07 wrote:
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>
>>What latency can we typical expect according to your best guess, when the system is not idle?
>>
>>Thanks,
>>Vincent
>
>I can't put a figure on it. It's just my experience from
>being around various hardware/software developments that
>the way to achieve low latency is to have few layers of
>protocol and be ruthless about keeping it simple. And CSI
>doesn't seem to have that flavor.
>

This is a hardware-level compensation circuit. Depending on how they implemented it, it could take as little as a few nanoseconds (since these are supposed to be multigigabit links, I would assume the data-rate per bit-line is close to the giga-bits-per-second range). How you would measure sub-clock differences in arrival time and then compensate for it could be done in many ways from very fast to very slow. Off the top of my head, I'd say a phase comparator between the clock line and each data line fed to a current-starved buffer. Such a thing would take one pulse from the transmitter to calibrate.