By: David Kanter (dkanter.delete@this.realworldtech.com), August 30, 2007 1:46 pm
Room: Moderated Discussions
Peter Gerdes (truepath@infiniteinjury.org) on 8/30/07 wrote:
---------------------------
>>No, I think you just misunderstood how the O state works.
>>
>>DK
>
>Pretty much as well as how the F state worked. Thanks for your explanation
>
>Still, I think my original question sorta stands. If you have processors with
>integrated memory controllers is saying that the cache line has to be written back
>to memory really much different from saying the processor owning that memory must
>be notified about the state of that cache line.
Yes. A write back to memory takes a long time relative to snooping the tags on your L1/L2 cache. You also waste memory bandwidth.
>In other words suppose CPU0 has a cache line in the M state and that CPU1 and CPU2
>both want to read that line (does any request without write hint force a write to
>memory?).
If you have a dirty cache line that 2+ CPUs want to read in Intel models, you must write that back. If they both want to write, then you're going to have to serialize the writes anyway...
>Now I understand this means there must be a logical write >to memory .
>However, if CPU0 integrates the controller for this memory >presumably this logical
>write is free. CPU0 needs only to internally mark the fact that this cache line
>has theoretically been written to memory and remember to do >so before eviction.
Nothing is truly free. A write to memory still uses up a WB buffer entry, takes power to execute and wastes bandwidth. It's not really a huge cost, which is probably why Intel didn't bother with that particular optimization.
>Similarly if CPU1 controls that memory address presumably (if the protocol allows
>it) you don't need to send the cache line from CPU0 to CPU1 >twice.
Every time someone snoops, everyone has to respond (even if they only respond with a NACK). So no matter what happens you are always wasting bandwidth on a cache miss.
DK
---------------------------
>>No, I think you just misunderstood how the O state works.
>>
>>DK
>
>Pretty much as well as how the F state worked. Thanks for your explanation
>
>Still, I think my original question sorta stands. If you have processors with
>integrated memory controllers is saying that the cache line has to be written back
>to memory really much different from saying the processor owning that memory must
>be notified about the state of that cache line.
Yes. A write back to memory takes a long time relative to snooping the tags on your L1/L2 cache. You also waste memory bandwidth.
>In other words suppose CPU0 has a cache line in the M state and that CPU1 and CPU2
>both want to read that line (does any request without write hint force a write to
>memory?).
If you have a dirty cache line that 2+ CPUs want to read in Intel models, you must write that back. If they both want to write, then you're going to have to serialize the writes anyway...
>Now I understand this means there must be a logical write >to memory .
>However, if CPU0 integrates the controller for this memory >presumably this logical
>write is free. CPU0 needs only to internally mark the fact that this cache line
>has theoretically been written to memory and remember to do >so before eviction.
Nothing is truly free. A write to memory still uses up a WB buffer entry, takes power to execute and wastes bandwidth. It's not really a huge cost, which is probably why Intel didn't bother with that particular optimization.
>Similarly if CPU1 controls that memory address presumably (if the protocol allows
>it) you don't need to send the cache line from CPU0 to CPU1 >twice.
Every time someone snoops, everyone has to respond (even if they only respond with a NACK). So no matter what happens you are always wasting bandwidth on a cache miss.
DK