I'm not too familiar with how the cache-line write-back of modern x86's are done but it makes sense to use a write-back immediately scheme in the case where a cache-line is stored in a memory pool connected to a third chip.

So let's say MPU0 stores a cache-line of modified data (C0) that belongs to MPU2. MPU1 and MPU3 then requests the cache-line and gets C0. At this point, there'd have to be multiple states if MPU0 were to avoid a write-back (one for the state inside MPU2 and one for the state inside MPU0) in addition to another state for data stored in MPU1 and MPU3.

Firing off a write-back command to MPU2 will update its cache with the modified data (C0) but, depending no how write-back commands are handled, doesn't necessarily mean that a memory write will occur. It simply means that MPU2 will get new data along with MPU1 and MPU3. MPU0 can then mark the cache-line as written back and never worry about it. It's then MPU2's job (which is convenient since it is directly tied to the physical memory that stores it) to respond with ACK's when a snoop occurs.

This naturally creates a situation when dirty cache-lines are handled by the MPU that is connected to the physical memory.