anonymous (a@b.c) on 9/17/07 wrote:
---------------------------
>Peter Gerdes (truepath@infiniteinjury.org) on 9/16/07 wrote:
>---------------------------
>>Why? So suppose that cache line L (in A's cache) corresponds to a memory location
>>in bank A and that as above B and C request to both read that location. The MESIF
>>protocol requires that A first write it's line out to memory and transitioning to
>>the F state before passing it on to B and C. But SINCE THE MEMORY CONTROLLER THAT
>>WOULD WRITE L TO MEMORY IS INTEGRATED INTO CHIP A NO ACTUAL WRITE HAS TO TAKE PLACE.
>>In other words A just *immediately* tells the other chips that it has written L
>>to memory and hands out the cache line to B and C making an *internal* mark to write
>>L to memory before eliminating it from it's own cache. Correctness is guaranteed
>>because the only way any other chip can read or write to the memory backing L is through chip A.
>>
>
>Seems to me that what you are saying is that "MESIF can have the advantages of
>MOESI if only it had the ability to put a cache line in a special state where it
>is shared with others but still dirty in the cache." But if I understand you correctly,
>that extra state is pretty dang close to what the "O" state is. In other words,
>you are suggesting MOESIF. So yes, you are right, you could do what you are suggesting,
>but it wouldn't be MESIF anymore. And as others have said, it would probably add
>quite a bit of complexity to go to MOESIF and not be much better than just plain MOESI.
>

Ahh, I think this is the real confusion. I'm assuming that MESIF and MOESI describe cache coherency *protocols*. That is they describe the protocol that any participating chips must adopt while talking to each other not how they must behave internally so long as this external protocol is honored.

I guess others here are assuming that MESIF and MOESI are terms that indicate how the chips actually behave not merely the protocol they expose to the other chips.