By: anon (no.delete@this.spam.com), September 23, 2007 10:53 am
Room: Moderated Discussions
David W. Hess (dwhess@banishedsouls.org) on 9/23/07 wrote:
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>David Kanter (dkanter@realworldtech.com) on 9/23/07 wrote:
>---------------------------
>>David W. Hess (dwhess@banishedsouls.org) on 9/22/07 wrote:
>>---------------------------
>>>anon (no@spam.com) on 9/22/07 wrote:
>>>---------------------------
>>>>>I suspect there is not a good reason to use 8B/10B encoding and sacrifice 20% of
>>>>>your throughput where a clock can be made available unless
>>>>
>>>>But if a clock signal were made available, then you'd be >>wasting 100% of the potential
>>>>throughput from that particular signal link, which could >>have been transferring data instead.
>>
>>>I had not considered that but both CSI and HT use one clock >lane per group of 4
>>>parallel data lanes yielding the same 80% efficiency.
>>
>>CSI uses 1 clock lane per 5 data lanes, and I was under the impression that HT used 1 clock lane per 8 data lanes...
>
>Sight is the second thing to go. I forget what the first is.
With HT's 1 clock link per 8 requirement, that would mean it "wastes" the potential data BW of 1 lane for every 8. While CSI wastes 1 for every 5. Either way HT seems to be more efficient in utilization of available data bandwidth (at face value).
>>>In the case of HT, the clock
>>>is required even when 8B/10B encoding is used to support AC >coupling.
>>
>>AC coupling is used for a box to box interconnect, right?
>
>That is what the specifications either say or imply. I suspect that the differential
>receiver common mode range is small enough that chassis ground differences can be
>great enough to cause problems. AC coupling support is suppose to be handled transparently.
>
>I am not completely clear what type of system configuration AMD has in mind that would require this.
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>David Kanter (dkanter@realworldtech.com) on 9/23/07 wrote:
>---------------------------
>>David W. Hess (dwhess@banishedsouls.org) on 9/22/07 wrote:
>>---------------------------
>>>anon (no@spam.com) on 9/22/07 wrote:
>>>---------------------------
>>>>>I suspect there is not a good reason to use 8B/10B encoding and sacrifice 20% of
>>>>>your throughput where a clock can be made available unless
>>>>
>>>>But if a clock signal were made available, then you'd be >>wasting 100% of the potential
>>>>throughput from that particular signal link, which could >>have been transferring data instead.
>>
>>>I had not considered that but both CSI and HT use one clock >lane per group of 4
>>>parallel data lanes yielding the same 80% efficiency.
>>
>>CSI uses 1 clock lane per 5 data lanes, and I was under the impression that HT used 1 clock lane per 8 data lanes...
>
>Sight is the second thing to go. I forget what the first is.
With HT's 1 clock link per 8 requirement, that would mean it "wastes" the potential data BW of 1 lane for every 8. While CSI wastes 1 for every 5. Either way HT seems to be more efficient in utilization of available data bandwidth (at face value).
>>>In the case of HT, the clock
>>>is required even when 8B/10B encoding is used to support AC >coupling.
>>
>>AC coupling is used for a box to box interconnect, right?
>
>That is what the specifications either say or imply. I suspect that the differential
>receiver common mode range is small enough that chassis ground differences can be
>great enough to cause problems. AC coupling support is suppose to be handled transparently.
>
>I am not completely clear what type of system configuration AMD has in mind that would require this.
