anon (no@spam.com) on 9/23/07 wrote:
---------------------------
>David W. Hess (dwhess@banishedsouls.org) on 9/23/07 wrote:
>---------------------------
>>David Kanter (dkanter@realworldtech.com) on 9/23/07 wrote:
>>---------------------------
>>>David W. Hess (dwhess@banishedsouls.org) on 9/22/07 wrote:
>>>---------------------------
>>>>anon (no@spam.com) on 9/22/07 wrote:
>>>>---------------------------

>>>CSI uses 1 clock lane per 5 data lanes, and I was under the impression that HT used 1 clock lane per 8 data lanes...
>>
>>Sight is the second thing to go. I forget what the first is.
>
>With HT's 1 clock link per 8 requirement, that would mean >it "wastes" the potential
>data BW of 1 lane for every 8. While CSI wastes 1 for >every 5. Either way HT seems
>to be more efficient in utilization of available data >bandwidth (at face value).

Several comments. First, I don't know what HT implementations actually look like. They may use more clocking lanes than required.

Second, the issue is not only utilization of data bandwidth, but power consumption. Bit lanes aren't free.

Third, the number of clocking lanes is a trade-off between power and data efficiency and design difficulty. With 5 data lanes per clock, the skew is going to be much less than with 8 data lanes per clock. The lower the skew the better for board designers. I don't know what the distribution of skew looks like (normal, pareto, uniform, etc.), but I think that any way you slice it, skew over 5 lanes is less than skew over 8. It's all a trade-off.

DK