By: Jonathan Kang (johnbk.delete@this.gmail.com), September 26, 2007 10:56 am
Room: Moderated Discussions
David W. Hess (dwhess@banishedsouls.org) on 9/26/07 wrote:
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>Jonathan Kang (johnbk@gmail.com) on 9/26/07 wrote:
>---------------------------
>>From what I've read of the various Rambus patents that seem to relate to this (7271623
>>and 7269706 are interesting in particular), it seems that they've been able to
>>cut power consumption by improving upon just about every component in a transmission
>>link in an iterative fashion. For instance, they've made a very sensitive receiver
>>that does selective amplification based on a reference clock to cut on transmission pre-emphasis power, etc.
>
>I browsed the patents. Isn't the later one from IBM?
Sorry, that should've been 7268706.
>High speed comparators often use this technique to prevent oscillation and/or lower
>power by becoming active only during the clock transition and then latching the output.
>
>I always found it interesting to see an analog comparator perform logic operations
>faster then the contemporary saturated logic. I do not remember them beating ECL though.
Transistors in non-saturation switch a lot faster than going back and forth between active and inactive regions. This is especially true for current-steering logic. The problem is you open yourself up to be much more sensitive to noise and latch-up problems.
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>Jonathan Kang (johnbk@gmail.com) on 9/26/07 wrote:
>---------------------------
>>From what I've read of the various Rambus patents that seem to relate to this (7271623
>>and 7269706 are interesting in particular), it seems that they've been able to
>>cut power consumption by improving upon just about every component in a transmission
>>link in an iterative fashion. For instance, they've made a very sensitive receiver
>>that does selective amplification based on a reference clock to cut on transmission pre-emphasis power, etc.
>
>I browsed the patents. Isn't the later one from IBM?
Sorry, that should've been 7268706.
>High speed comparators often use this technique to prevent oscillation and/or lower
>power by becoming active only during the clock transition and then latching the output.
>
>I always found it interesting to see an analog comparator perform logic operations
>faster then the contemporary saturated logic. I do not remember them beating ECL though.
Transistors in non-saturation switch a lot faster than going back and forth between active and inactive regions. This is especially true for current-steering logic. The problem is you open yourself up to be much more sensitive to noise and latch-up problems.
