By: Jonathan Kang (johnbk.delete@this.gmail.com), September 27, 2007 7:16 am
Room: Moderated Discussions
rwessel (robertwessel@yahoo.com) on 9/26/07 wrote:
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>Jonathan Kang (johnbk@gmail.com) on 9/26/07 wrote:
>---------------------------
>>This does not, however, get around the fundamental issue of the link having to
>>be active at all times. Remember that whatever power figures given for parallel
>>links such as CSI are only the active power figures. When comparing it to a serialized
>>link, even a low-powered one like the one Rambus has, one has to take into account average power.
>
>
>OTOH, you can (at least in theory) turn off all but one of the parallel serial
>links, and still have quick (low latency) access, and the full bandwidth is "only"
>a few hundred clocks away. Obviously you could do the whole power vs. load tradeoff on a dynamic basis.
That's a good point. Yes, in the situation of multiple, parallel links, all but one can be turned off. But for schemes such as cache coherency, bursts of large (or small) chunks of data would need to be transmitted as fast as possible.
For instance, if the link between 3 MPU's are in the idle state (only 1 link active) and a snoop is made. If the response is that the cache data must be updated, then that cache data must be transmitted over the link as quickly as possible to prevent stalls. This isn't possible unless the link can go between idle (low bandwidth) and active (full bandwidth) within a matter of a few cycle times.
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>Jonathan Kang (johnbk@gmail.com) on 9/26/07 wrote:
>---------------------------
>>This does not, however, get around the fundamental issue of the link having to
>>be active at all times. Remember that whatever power figures given for parallel
>>links such as CSI are only the active power figures. When comparing it to a serialized
>>link, even a low-powered one like the one Rambus has, one has to take into account average power.
>
>
>OTOH, you can (at least in theory) turn off all but one of the parallel serial
>links, and still have quick (low latency) access, and the full bandwidth is "only"
>a few hundred clocks away. Obviously you could do the whole power vs. load tradeoff on a dynamic basis.
That's a good point. Yes, in the situation of multiple, parallel links, all but one can be turned off. But for schemes such as cache coherency, bursts of large (or small) chunks of data would need to be transmitted as fast as possible.
For instance, if the link between 3 MPU's are in the idle state (only 1 link active) and a snoop is made. If the response is that the cache data must be updated, then that cache data must be transmitted over the link as quickly as possible to prevent stalls. This isn't possible unless the link can go between idle (low bandwidth) and active (full bandwidth) within a matter of a few cycle times.
