By: rwessel (robertwessel.delete@this.yahoo.com), September 27, 2007 1:20 pm
Room: Moderated Discussions
Jonathan Kang (johnbk@gmail.com) on 9/27/07 wrote:
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>That's a good point. Yes, in the situation of multiple, parallel links, all but
>one can be turned off. But for schemes such as cache coherency, bursts of large
>(or small) chunks of data would need to be transmitted as fast as possible.
>
>For instance, if the link between 3 MPU's are in the idle state (only 1 link active)
>and a snoop is made. If the response is that the cache data must be updated, then
>that cache data must be transmitted over the link as quickly as possible to prevent
>stalls. This isn't possible unless the link can go between idle (low bandwidth)
>and active (full bandwidth) within a matter of a few cycle times.
That's true, but that largely going to be a self limiting problem - if the CPU is idle, it may be a bit slow in responding to actual cache line updates/writebacks/whatever (just the coherency checks themselves should have plenty of bandwidth with a single link), and there will be a limited number of times a cache line will need to be transferred off the idle CPU.
Obviously if the CPU has the memory controller, there's going to be a lot of real traffic, even if the CPU is idle, but even in that case some of the links can probably be shut down with minimal impact on the system, since the traffic from the CPU is simply not going to be there.
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>That's a good point. Yes, in the situation of multiple, parallel links, all but
>one can be turned off. But for schemes such as cache coherency, bursts of large
>(or small) chunks of data would need to be transmitted as fast as possible.
>
>For instance, if the link between 3 MPU's are in the idle state (only 1 link active)
>and a snoop is made. If the response is that the cache data must be updated, then
>that cache data must be transmitted over the link as quickly as possible to prevent
>stalls. This isn't possible unless the link can go between idle (low bandwidth)
>and active (full bandwidth) within a matter of a few cycle times.
That's true, but that largely going to be a self limiting problem - if the CPU is idle, it may be a bit slow in responding to actual cache line updates/writebacks/whatever (just the coherency checks themselves should have plenty of bandwidth with a single link), and there will be a limited number of times a cache line will need to be transferred off the idle CPU.
Obviously if the CPU has the memory controller, there's going to be a lot of real traffic, even if the CPU is idle, but even in that case some of the links can probably be shut down with minimal impact on the system, since the traffic from the CPU is simply not going to be there.