By: David Kanter (dkanter.delete@this.realworldtech.com), September 23, 2007 12:46 pm
Room: Moderated Discussions
jigal (jigal2@gmail.com) on 9/23/07 wrote:
---------------------------
>Thanx for the reply.
>
>Pretty much overwhelmed by the the level of technical >details - since I am not a vlsi guy, but merely a s/w guy.
>The reason I am asking, is that, after all, Intel invested
>considerable effort in adding the AS layer on top of the
>PCI-E, which seems to turn it to a full networking layer,
>which CSI also seems to add.
>(although you could argue that "Intel" in this sense is a
>bunch of engineers toying with their own standard...)
So I don't actually know much about advanced switching (PCI-AS), except that it has been de-emphasized (i.e. doomed to irrelevancy).
>This is in contrast to AMD which has a consistent on board
>p2p link - the HT link, which seems to be PCI friendly,
>and was invented when PCI-E wasn't relevant, I guess.
>I remember reading an pdf on their website trying to
>differentiate HT from PCI as on intra board links vs.
>inter-board links, or even inter-chassis, etc...
>Is the HT used for coherency protocols between AMD asics?
A variant of HT is used for coherency.
>And regardless, now that we have a new guy in town,
>what is the future of PCI-E, if they're not going to
>add coherency protocols on top of it?
PCI-E will be used for the same thing it was before. The way to think about it is that CSI will replace the front-side bus, and whatever link was between the Northbridge and Southbridge of the chipset.
PCI-E ran from the NB or SB to peripherals and is unaffected.
DK
---------------------------
>Thanx for the reply.
>
>Pretty much overwhelmed by the the level of technical >details - since I am not a vlsi guy, but merely a s/w guy.
>The reason I am asking, is that, after all, Intel invested
>considerable effort in adding the AS layer on top of the
>PCI-E, which seems to turn it to a full networking layer,
>which CSI also seems to add.
>(although you could argue that "Intel" in this sense is a
>bunch of engineers toying with their own standard...)
So I don't actually know much about advanced switching (PCI-AS), except that it has been de-emphasized (i.e. doomed to irrelevancy).
>This is in contrast to AMD which has a consistent on board
>p2p link - the HT link, which seems to be PCI friendly,
>and was invented when PCI-E wasn't relevant, I guess.
>I remember reading an pdf on their website trying to
>differentiate HT from PCI as on intra board links vs.
>inter-board links, or even inter-chassis, etc...
>Is the HT used for coherency protocols between AMD asics?
A variant of HT is used for coherency.
>And regardless, now that we have a new guy in town,
>what is the future of PCI-E, if they're not going to
>add coherency protocols on top of it?
PCI-E will be used for the same thing it was before. The way to think about it is that CSI will replace the front-side bus, and whatever link was between the Northbridge and Southbridge of the chipset.
PCI-E ran from the NB or SB to peripherals and is unaffected.
DK
