Next Generation zSeries CPU Slideshow

By: rwessel (robertwessel.delete@this.yahoo.com), October 15, 2007 9:44 pm
Room: Moderated Discussions
Interesting stuff:

http://www2.hursley.ibm.com/decimal/IBM-z6-mainframe-microprocessor-Webb.pdf

Highlights:

- “z6” CPU is not a Power6, but shares significant technology and elements, including parts of caches, interconnects and functional units and overall pipeline design – “Siblings, not identical twins”

- Executes 668 of 894 architected zSeries instructions in hardware, the rest trap to millicode, as do existing zSeries CPUs. Includes 50 new zSeries instructions. New support for 1MB page frames (weird – 2MB would fit the current page tables much better).

- Quad core, “mostly in-order design,” shades of P6. z990 and z9 were fairly traditional OoO dual cores.

- Instructions are issued in groups of unspecified size.

- 4Ghz and 15 FO4, vs. 1.7GHz and 28FO4

- 14 stage pipeline (similar to P6), contrasting with z9 at approximately 6. In order fast design obviously impacts some things, but many operations seem to come out well ahead: fix point operation forwarding loop in pipeline is 1 cycle in both z9 and z6, but nets 15 vs. 28FO4 in new z6. Load-load latency increase from 3 to 4, but z6 FO4 times are 60 vs 84 for z9. Mispredicted branches take a big hit, as expected for an in-order design – 13+ cycles vs. 6+ for z9 (195+ FO4 vs. 168+).

- 434mm**2 die, 991M transistors, 8765 pin “package”

- 64KB L1I, 128KB L1D and 3MB private L2 per core, off chip L3 (24MB on hub chip – 48MB on two – apparent build option). Directory based coherence.

- “Aggressive branch prediction”

- Multi-level TLB as on z9

- I/Os: 4x48GB/s interprocessor, 4x13GB/s memory, 2x17GP. The interprocessor and memory interface look to be the same as P6’s, and the I/O may be as well.

- Traditional decimal math now routed through decimal FP unit. DFP is now fully supported in hardware (z9 was mostly millicode), and the DFP unit is largely identical to the P6’s.

- Compression and encryption accelerators – shared by pairs of cores.

- Traditional zSeries RAS features in addition to the P6 stuff, including a checklpoint buffer to periodically record the full architected CPU state to allow retry or state migration in the even of failure. “Over 20,000 error checkers in chip”

- New focus on energy efficiency

All in all, this looks like the most radically different zSeries core in decades.
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TopicPosted ByDate
Next Generation zSeries CPU Slideshowrwessel2007/10/15 09:44 PM
  Next Generation zSeries CPU SlideshowDavid Kanter2007/10/15 09:53 PM
    Next Generation zSeries CPU Slideshowrwessel2007/10/15 10:21 PM
  Next Generation zSeries CPU SlideshowDevon Welles2007/10/15 11:10 PM
    Next Generation zSeries CPU Slideshowhobel2007/10/17 06:52 AM
      memory bandwidthhobel2007/10/25 12:40 AM
  Nice findjesper Frimann2007/10/15 11:32 PM
  Next Generation zSeries CPU SlideshowDean Kent2007/10/16 02:44 AM
    Next Generation zSeries CPU Slideshowrwessel2007/10/16 02:30 PM
  Next Generation zSeries CPU SlideshowMichael S2007/10/16 08:10 AM
    Next Generation zSeries CPU SlideshowDean Kent2007/10/16 08:57 AM
      Next Generation zSeries CPU SlideshowMichael S2007/10/16 10:39 AM
        Obscure implementation detail of nearly obsolete CPU; disregard :-)Konrad Schwarz2007/10/16 12:24 PM
          Obscure implementation detail of nearly obsolete CPU; disregard :-)rwessel2007/10/16 02:37 PM
            Obscure implementation detail of nearly obsolete CPU; disregard :-)Gabriele Svelto2007/10/16 11:13 PM
            Obscure implementation detail of nearly obsolete CPU; disregard :-)Konrad Schwarz2007/10/17 10:12 AM
              Obscure implementation detail of nearly obsolete CPU; disregard :-)rwessel2007/10/17 11:26 AM
                Obscure implementation detail of nearly obsolete CPU; disregard :-)Potatoswatter2007/10/18 08:49 AM
                  Obscure implementation detail of nearly obsolete CPU; disregard :-)rwessel2007/10/18 01:03 PM
                    Obscure implementation detail of nearly obsolete CPU; disregard :-)anonymous422007/10/18 03:42 PM
          Obscure implementation detail of nearly obsolete CPU; disregard :-)Rob Thorpe2007/10/17 01:25 AM
        Next Generation zSeries CPU Slideshowrwessel2007/10/16 02:44 PM
          Next Generation zSeries CPU SlideshowMichael S2007/10/16 03:37 PM
            Next Generation zSeries CPU Slideshowrwessel2007/10/16 03:49 PM
              Next Generation zSeries CPU Slideshowrwessel2007/10/16 03:52 PM
                Thank you (NT)Michael S2007/10/16 04:11 PM
          z6 RASDavid Kanter2007/10/16 04:59 PM
  Next Generation zSeries CPU SlideshowMichael S2007/10/16 04:08 PM
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