>>>>>>Intel will present two papers on Tukwila, the 65nm Itanium microprocessor. The first (4.6) is a general overview that describes the design as a 699mm2 die with four dual threaded cores, 30MB of cache a memory controller with 34GB/s of bandwidth and 96GB/s of processor interconnect bandwidth.<<<<<<

>>30MB of cache
6MB L3 per core
1MB L2 I-cache per core
256K L2 D-cache per core
256K L1 cache per core (128K each I/D)

Makes 30MB. Maybe? No?


>>a memory controller with 34GB/s of bandwidth

Quad-channel DDR3-1066?




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