David Kanter (dkanter@realworldtech.com) on 12/9/07 wrote:
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>IntelUser2000 (Intel_user2000@yahoo.ca) on 12/9/07 wrote:
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>>anon (anon@anon.com) on 12/9/07 wrote:
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>>>IntelUser2000 (Intel_user2000@yahoo.ca) on 12/9/07 wrote:
>>>
>>>>David, can you get more information on Silverthorne?? Any architectural details??
>>>>This seems like a completely new architecture. I thought it would be somewhat based off Banias.
>>>
>>>http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=199100535
>>>
>>
>>Thanks, but I already know that. I want the technical >details. Cache latency, possible
>>performance values, does it have things like uop fusion >etc, power management features.
>>All the things that ISSCC will bring. I can't wait :).
>
>I have a lot of guesses, but I think it's better that I hold onto them at this point.
>
>The good news is that the chair of the Mobile Processing session from ISSCC isn't
>from Intel. In general, I suspect this means that they will have to disclose more
>technical information and stay away from marketing.
>
>DK

I found ever slight more details on the chip. The VLSI Seminar announcements detail show little more than the one from ISSCC:

http://dropzone.tamu.edu/VLSISeminars

"This presentation will describe a low power Intel(r) Architecture (IA) processor specifically designed for Ultra-Mobile PCs where average power consumed is in the order of a few hundred mW with performance similar to mainstream Ultra-Mobile PCs. The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32KB instruction and 24KB data L1 caches, independent integer and floating point execution units, x86 front end execution unit, a 512KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47M transistors in a die size under 25 mm2 manufactured in a 9-metal 45nm CMOS process with optimized transistors for low leakage packaged in a Halide-Free 441 ball, 14X13 mm uFCBGA. Thermal Design Power (TDP) consumption is measured at 2W using a synthetic power-virus test at a frequency of 2GHz."

New info:
-uFCBGA is at 14x13 mm
-533MT/s dual-mode(GTL and CMOS, is this somehow different??)
-2W with synthetic power-virus test at 2GHz

It says its a 2007 seminar, why is the info not out yet??