David Wang's IEDM Article now available

Article: Process Technology Advancements at IEDM 2007
By: David Wang (dwang.delete@this.not.here.com), January 22, 2008 8:26 pm
Room: Moderated Discussions
Potatoswatter (potswa_mac@nospam.com) on 1/22/08 wrote:
---------------------------
>IntelUser2000 (Intel_user2000@yahoo.ca) on 1/22/08 wrote:
>---------------------------
>>David Wang (dwang@not.here.com) on 1/21/08 wrote:
>>---------------------------
>>>Anders Jensen (@.) on 1/21/08 wrote:
>>>---------------------------
>>>>Nice article! Thanks a lot. Just wondering about on thing.
>>>>
>>>>Updated Process Technology Cross Comparison chart shows a value of just 1 nm for
>>>>"high performance/Intel/2007/t_ox". I thought the t_ox value of Intel's 45 nm was
>>>>much more than 1 nm due to its High-k materials.
>>>
>>>Good catch.
>>>
>>>One caveat is that there's no standard way of measuring tox, so just take the self-reported
>>>tox numbers with a grain of salt. More as a general reference than anything really useful.
>>>
>>>However, more importantly to the point here is that I forgot to add a footnote
>>>to Intel's reported tox number on 45 nm - it's reported in units of EOT (equivalent
>>>oxide thickness), not physical thickness. That was a question I noted down to go
>>>back and chase down, but never did. I will take a note to see if Intel will give
>>>out the physical gate thickness on the 45 nm process.
>>>
>>>David
>>>
>>
>>I know quite long time ago when Intel first demonstrated High-K Metal gate devices,
>>they said the tox was 3.0nm. Perhaps they are using similar thickness...
>
>Demonstration technology might not be so strongly correlated to the final thing.
>3 nm sounds thick enough to be reliable to me, but what do I know?

Semiconductor.net has a nice article on the topic that cites Kaizad Mistry of Intel.

The hafnium-based gate dielectric has a 1 nm equivalent oxide thickness (EOT) for both n- and p-type transistors, with a 7 Å interfacial layer, which Mistry referred to as a "transition layer." Although Intel does not provide its inversion thickness, Mistry said in an interview that the difference between the EOT and Tinv "is about 4 Å, plus or minus 1." The physical thickness of the high-k layer was 18–20 Å, which is thick enough to provide what Mistry said was a 25× improvement in NMOS leakage current, compared with SiO2, and a three orders of magnitude (1000×) improvement in PMOS leakage.

http://www.semiconductor.net/article/CA6516289.html

>It seems a silly parameter to use an "equivalent" for, but whatever. Who really
>needs more than Igate, Vt, Vbreakdown :v) . It's nice that there's room to make it much thinner in the future.
>
>And Dave, thanks a ton for compiling that table!

No problem. Makes it easier to put everyone on "equal footing", as much as that is possible.


< Previous Post in Thread 
TopicPosted ByDate
David Wang's IEDM Article now availableDavid Kanter2008/01/20 10:43 PM
  David Wang's IEDM Article now availableDoug Siebert2008/01/21 12:02 AM
    David Wang's IEDM Article now availableDavid Wang2008/01/21 01:00 PM
      David Wang's IEDM Article now availableAlberto2008/01/21 02:40 PM
    David Wang's IEDM Article now availableAlberto2008/01/21 03:24 PM
  David Wang's IEDM Article now availablejumpingjack2008/01/21 01:07 AM
  David Wang's IEDM Article now availableAnders Jensen2008/01/21 02:15 AM
    David Wang's IEDM Article now availableDavid Wang2008/01/21 12:36 PM
      David Wang's IEDM Article now availableIntelUser20002008/01/22 04:28 AM
        David Wang's IEDM Article now availablePotatoswatter2008/01/22 06:18 AM
          David Wang's IEDM Article now availableDavid Wang2008/01/22 08:26 PM
Reply to this Topic
Name:
Email:
Topic:
Body: No Text
How do you spell avocado?