Article: ISSCC 2008 Cell Processor Update
By: David Kanter (dkanter.delete@this.realworldtech.com), February 25, 2008 1:08 am
Room: Moderated Discussions
Hi Everyone,
David Wang just finished up a great summary of IBM's presentation at ISSCC 2008 regarding their 3rd generation of the CELL microprocessor.
http://www.realworldtech.com/page.cfm?ArticleID=RWT022508002434&p=1
I'd like to thank David for taking the time from his busy schedule to attend ISSCC and write up this presentation (he's way ahead of me in that regard).
Personally, I found that the 45nm CELL presentation was very interesting, since the optimization target that many focus on (GHz) is irrelevant. The beauty/challenge of designing a console is that once you commit to a frequency, you cannot use chips any slower or faster. Instead, fast chips might be used at a lower voltage bin, etc. Given this situation, it's interesting to see the approach that IBM's engineers took - especially given the constraints of IBM's 45nm process.
Enjoy,
David
David Wang just finished up a great summary of IBM's presentation at ISSCC 2008 regarding their 3rd generation of the CELL microprocessor.
http://www.realworldtech.com/page.cfm?ArticleID=RWT022508002434&p=1
I'd like to thank David for taking the time from his busy schedule to attend ISSCC and write up this presentation (he's way ahead of me in that regard).
Personally, I found that the 45nm CELL presentation was very interesting, since the optimization target that many focus on (GHz) is irrelevant. The beauty/challenge of designing a console is that once you commit to a frequency, you cannot use chips any slower or faster. Instead, fast chips might be used at a lower voltage bin, etc. Given this situation, it's interesting to see the approach that IBM's engineers took - especially given the constraints of IBM's 45nm process.
Enjoy,
David