Article: ISSCC 2008 Cell Processor Update
By: David Wang (dwang.delete@this.not.here.com), February 25, 2008 10:59 am
Room: Moderated Discussions
slacker (s@lack.er) on 2/25/08 wrote:
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>Were the XDR I/O cells shrunk at all? I would imagine that the I/O cells were designed
>by Rambus and provided to IBM as hard IP (GDS-II). If the cells weren't shrunk at
>all from 65nm, I'd be inclined to believe this is either because Rambus failed to
>shrink the circuits to operate on IBM's 45nm process, or because IBM didn't want to pay Rambus for the service.
Funny enough, I can't remember now having asked that specific question to the presenter, but we talked about the I/O stuff for a bit. Basically,
1. I/O circuits don't scale well.
2. Pads and bumps have to be at or near the same places because the package ballout stayed the same (minimize system impact).
So I'm not sure if they even tried to shrink the XDR stuff because the benefit (smaller die area) would have been a lot less than what could be gotten from logic shrink. Moreover, the primary target was lower power, and re-doing the XDR stuff for 45 nm wouldn't get you much of anything there.
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- "The fundamental issue is that in the desire to minimize design effort and
>maintain the basic floorplan, the scalability of the processor as a whole is constrained
>by the scalability of the least-scalable basic blocks. As to be expected, the least
>scalable basic blocks are the I/Os: Rambus FlexIO and XDRAM Interfaces. This
>is due to the nature of I/O interfaces that have specific connectivity requirements,
>not due to anything that can be blamed on Rambus."
>
>Were the XDR I/O cells shrunk at all? I would imagine that the I/O cells were designed
>by Rambus and provided to IBM as hard IP (GDS-II). If the cells weren't shrunk at
>all from 65nm, I'd be inclined to believe this is either because Rambus failed to
>shrink the circuits to operate on IBM's 45nm process, or because IBM didn't want to pay Rambus for the service.
Funny enough, I can't remember now having asked that specific question to the presenter, but we talked about the I/O stuff for a bit. Basically,
1. I/O circuits don't scale well.
2. Pads and bumps have to be at or near the same places because the package ballout stayed the same (minimize system impact).
So I'm not sure if they even tried to shrink the XDR stuff because the benefit (smaller die area) would have been a lot less than what could be gotten from logic shrink. Moreover, the primary target was lower power, and re-doing the XDR stuff for 45 nm wouldn't get you much of anything there.
