Article: ISSCC 2008 Cell Processor Update
By: slacker (s.delete@this.lack.er), February 25, 2008 4:14 pm
Room: Moderated Discussions
David Wang (dwang@not.here.com) on 2/25/08 wrote:
---------------------------
>Funny enough, I can't remember now having asked that specific question to the presenter,
>but we talked about the I/O stuff for a bit. Basically,
>
>1. I/O circuits don't scale well.
>
>2. Pads and bumps have to be at or near the same places because the package ballout
>stayed the same (minimize system impact).
>
>So I'm not sure if they even tried to shrink the XDR stuff because the benefit
>(smaller die area) would have been a lot less than what could be gotten from logic
>shrink. Moreover, the primary target was lower power, and re-doing the XDR stuff
>for 45 nm wouldn't get you much of anything there.
It now strikes me as obvious that the I/O cells have been shrunk from the 65nm design. From your article, the chip dimensions are:
65nm - 15.59 x 11.20 [mm^2]
45nm - 12.75 x 9.06 [mm^2]
By looking at die photos, it looks like the I/O cells stretch across the entire height of both designs. The simple conclusion is that the cells have been shrunk vertically from 11.20mm to 9.06mm.
http://www.trustedreviews.com/images/article/inline/6744-ibmcell.jpg
http://www.realworldtech.com/includes/images/articles/45nm-cell-3.gif
I am not convinced by the argument that the package ballout would limit the scaling of the I/O cells. From your article, the C4 bumps were redistributed after power analysis, so IBM would have to develop another package, anyway.
You are right that I/O scaling is difficult, and it's often hard to shrink the total area of the I/O cells. But it's not the total area which is the big concern to me, but the aspect ratio. It just strikes me as really odd that the cells weren't redone with a longer aspect ratio to accommodate for the overall floorplan. Maybe Rambus couldn't achieve this, maybe IBM gave them a conservative estimate for chip height and couldn't update them until it was too late. Maybe IBM just took the hard IP from Rambus and did a quick-n-dirty shrink themselves. I suppose that, in the end, the wasted space is not defectable area, so perhaps the area (cost)-savings for I/O redesign simply wasn't worth it.
---------------------------
>Funny enough, I can't remember now having asked that specific question to the presenter,
>but we talked about the I/O stuff for a bit. Basically,
>
>1. I/O circuits don't scale well.
>
>2. Pads and bumps have to be at or near the same places because the package ballout
>stayed the same (minimize system impact).
>
>So I'm not sure if they even tried to shrink the XDR stuff because the benefit
>(smaller die area) would have been a lot less than what could be gotten from logic
>shrink. Moreover, the primary target was lower power, and re-doing the XDR stuff
>for 45 nm wouldn't get you much of anything there.
It now strikes me as obvious that the I/O cells have been shrunk from the 65nm design. From your article, the chip dimensions are:
65nm - 15.59 x 11.20 [mm^2]
45nm - 12.75 x 9.06 [mm^2]
By looking at die photos, it looks like the I/O cells stretch across the entire height of both designs. The simple conclusion is that the cells have been shrunk vertically from 11.20mm to 9.06mm.
http://www.trustedreviews.com/images/article/inline/6744-ibmcell.jpg
http://www.realworldtech.com/includes/images/articles/45nm-cell-3.gif
I am not convinced by the argument that the package ballout would limit the scaling of the I/O cells. From your article, the C4 bumps were redistributed after power analysis, so IBM would have to develop another package, anyway.
You are right that I/O scaling is difficult, and it's often hard to shrink the total area of the I/O cells. But it's not the total area which is the big concern to me, but the aspect ratio. It just strikes me as really odd that the cells weren't redone with a longer aspect ratio to accommodate for the overall floorplan. Maybe Rambus couldn't achieve this, maybe IBM gave them a conservative estimate for chip height and couldn't update them until it was too late. Maybe IBM just took the hard IP from Rambus and did a quick-n-dirty shrink themselves. I suppose that, in the end, the wasted space is not defectable area, so perhaps the area (cost)-savings for I/O redesign simply wasn't worth it.
