Article: ISSCC 2008 Cell Processor Update
By: slacker (s.delete@this.lack.er), February 25, 2008 8:30 pm
Room: Moderated Discussions
David Wang (dwang@not.here.com) on 2/25/08 wrote:
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>>>2. Pads and bumps have to be at or near the same places because the package ballout
>>>stayed the same (minimize system impact).
>>
>>I am not convinced by the argument that the package ballout would limit the scaling
>>of the I/O cells. From your article, the C4 bumps were redistributed after power
>>analysis, so IBM would have to develop another package, anyway.
>
>Yes, they had to develope a different package, but to use the same packaging technology,
>they wanted to use the same bump pitch, so you can move the bumps around, just can't
>move them closer together much more. Changing the aspect ratio would be somewhat limited by that constraint.
While I agree that the package ballout could be a constraint to the chip layout in this regard, it also seems unlikely to me. Consider the levels which the signals must traverse:
IBM has exactly one fixed constraint here: the positioning of the package balls. Everything else can be changed. The further you go down this hierarchy (to the left), the more freedom you have to move things around. This freedom is expanded when you consider the fact that the chip itself is shrinking. Consider the following layout:
http://i26.tinypic.com/x4ohe0.png
When you shrink the chip, you're usually given more area available for the routing. In the case of the 45nm Cell, this routing would be done on the package substrate itself. This is why it's hard for me to accept that the package ballout was a significant constraint to the layout of the I/O cells.
>As I wrote, the basic floorplan had to remain unchanged, and changing the aspect
>ratio of the rambus blocks would probably require quite a bit of hand place/route/adjustment,
>and that would seem to be against the philosophy of the quick and dirty automated shrink.
Originally, I didn't grasp that there was only ten work-years worth of effort put in to the shrink. When I consider that, all inefficiencies in layout are explained. I don't even know how you could shrink a chip of this magnitude with such little time investment. The automation required would be phenomenal.
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>>>2. Pads and bumps have to be at or near the same places because the package ballout
>>>stayed the same (minimize system impact).
>>
>>I am not convinced by the argument that the package ballout would limit the scaling
>>of the I/O cells. From your article, the C4 bumps were redistributed after power
>>analysis, so IBM would have to develop another package, anyway.
>
>Yes, they had to develope a different package, but to use the same packaging technology,
>they wanted to use the same bump pitch, so you can move the bumps around, just can't
>move them closer together much more. Changing the aspect ratio would be somewhat limited by that constraint.
While I agree that the package ballout could be a constraint to the chip layout in this regard, it also seems unlikely to me. Consider the levels which the signals must traverse:
- chip transistors <-> C4 <-> package bonding pads <-> package balls
IBM has exactly one fixed constraint here: the positioning of the package balls. Everything else can be changed. The further you go down this hierarchy (to the left), the more freedom you have to move things around. This freedom is expanded when you consider the fact that the chip itself is shrinking. Consider the following layout:
http://i26.tinypic.com/x4ohe0.png
When you shrink the chip, you're usually given more area available for the routing. In the case of the 45nm Cell, this routing would be done on the package substrate itself. This is why it's hard for me to accept that the package ballout was a significant constraint to the layout of the I/O cells.
>As I wrote, the basic floorplan had to remain unchanged, and changing the aspect
>ratio of the rambus blocks would probably require quite a bit of hand place/route/adjustment,
>and that would seem to be against the philosophy of the quick and dirty automated shrink.
Originally, I didn't grasp that there was only ten work-years worth of effort put in to the shrink. When I consider that, all inefficiencies in layout are explained. I don't even know how you could shrink a chip of this magnitude with such little time investment. The automation required would be phenomenal.
