SSE 4.2

By: Michael S (, March 19, 2008 4:13 pm
Room: Moderated Discussions
Ian Ollmann ( on 3/19/08 wrote:
>Doug Siebert ( on 3/18/08 wrote:
>>Another thing I was interested to see in Nehalem was the SSE 4.2 support for string
>>instructions. Somehow that doesn't surprise me, if for no other reason than the
>>Google vs. Microsoft War of the Datacenters.
>What surprises me is that they chose to release them under the SSE name. None of
>these are vector instructions. (Maybe they are long vectors?) Certainly Intel has
>introduced non-vector ISA additions in SSE before (FISTTP in SSE3) but that was
>one scalar instruction out of many vector instructions. They seem to have no vehicle
>other than SSE to introduce new ISA.

5 out of 7 SSE 4.2 instructions (4 text/string processing ops + 1 Packed Comparison op) operate on 128-bit XMM registers in typical SIMD manner exactly like a bulk of older SSEx. So they are called SSE by right.

The remaining couple of instructions (CRC32 and POPCNT) operates on GPRs and really have nothing to do with SIMD. The presence of POPCNT is marked by separate bit in CPUID so it is likely that in the final documentation POPCNT would not be considered a part of SSE 4.2

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