CMPXCHG latency

By: Linus Torvalds (, March 29, 2008 11:43 am
Room: Moderated Discussions
David Kanter ( on 3/28/08 wrote:
>Normal data memory, aligned access and present in TLBs with
>the appropriate accesses...

Stupid test-program. No guarantees. This one is probably
one or two cycles more than the actual instruction takes,
because I included the (miniscule) loop overhead here too.

Core 2:
lock add: 27 cycles
lock cmpxchg: 31 cycles

P4 (pre-prescott):
lock addl: 124 cycles
lock cmpxchg: 137 cycles

lock add: 15 cycles
lock cmpxchg: 17 cycles

Those P4 numbers may sound horrible, but trust me, there
are things the P4 does even more badly at. And I think
Prescott is probably a few cycles worse.

So ignore the P4 numbers. They aren't even interesting.

But I'd really like to stress that those are not guaranteed
to be cycle-accurate. They're close but that's all
I will guarantee. In particular, I bet it changes a lot if
you have lots of other stores in flight in the store buffer
etc, so the real-life numbers will likely depend on the
code around the locked instruction.

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