CMPXCHG latency

By: David W. Hess (dwhess.delete@this.banishedsouls.org), March 29, 2008 11:56 am
Room: Moderated Discussions
Linus Torvalds (torvalds@linux-foundation.org) on 3/29/08 wrote:
---------------------------
>P4 (pre-prescott):
>lock addl: 124 cycles
>lock cmpxchg: 137 cycles
>
> . . .
>
>Those P4 numbers may sound horrible, but trust me, there
>are things the P4 does even more badly at. And I think
>Prescott is probably a few cycles worse.
>
>So ignore the P4 numbers. They aren't even interesting.

My own small efforts at searching turned up P4 numbers in the 130 to 160 clock cycle range so you must be close. I did not find anything for Core or Core2.
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