CMPXCHG latency

By: Linus Torvalds (, March 29, 2008 2:17 pm
Room: Moderated Discussions
Linus Torvalds ( on 3/29/08 wrote:
>Core 2:
>lock add: 27 cycles
>lock cmpxchg: 31 cycles

Side note: what I will find interesting is whether
Nehalem gets this down to just "K8 levels" (ie cuts the
cycles in half), or whether it gets it down to "non-
locked" performance levels (at which point the cost of
an individual instruction is basically not measurable,
because it's pipelined and depends almost entirely on
what is around it).

So with my stupid test-program, if I test non-locked ops,
I get

Core 2:
addl: 6 cycles (RAW hazard)
2 cycles (no hazard)
cmpxchg: 10 cycles (RAW hazard)
7 cycles (no hazard)

but at that point it is all due to a RAW-hazard kicking
in on the mem-to-mem RMW (together with cmpxchg just being
four cycles slower).

IOW, it's 6 cycles just because I do a tight loop of RMW
operations to the same memory location - if I do it to
an array of memory locations, the cost goes down to just
two cycles (and that includes the loop overhead itself:
an empty loop is one cycle).

With the locked ops, you don't see that behavior, because
the locked ops in Core 2 don't pipeline.

So what I'm going to be very interested in is whether the
locked ops work without flushing the pipeline in Nehalem.
Do we get down from 27 cycles to just single cycles? Or
does it stay in the teens?

If Intel really will be able to pipeline the thing, I'll
be very happy. Spinlocks will still end up being
very expensive for the cache-bouncing case, but they'd
be basically free for the non-contended case.

We'll know soon enough, I guess. If anybody has early
silicon and runs Linux on it, I can send my trivial test-
program ;)

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