CMPXCHG latency

By: nick (, March 31, 2008 7:34 pm
Room: Moderated Discussions
Aaron Spink ( on 3/31/08 wrote:
>Linus Torvalds ( on 3/31/08 wrote:
>>Michael S ( on 3/31/08 wrote:
>>>Non-contended spinlock doesn't mean the absence of cache-
>>>bouncing. I'd guess that in majority of practical cases you
>>>will see a combination of very low contention rate with
>>>high (or, when the number of threads exceeds two, very
>>>high) cache-bouncing rates.
>>There are lots of very common cases where you have
>>absolutely no cache contention or bouncing at all in
>>Any piece of code that is thread-safe has to have locking,
>>but a lot of it is then not used with threads at all, or
>>has the threads idle - waiting for some event.
>>This includes some very basic code like core library code,
>>and under many loads that code is hot and critical. Think
>>about something as fundamental as just "malloc()", and
>>think about the fact that the same library code is used
>>for both threaded and non-threaded applications.
>>And even for things like a kernel, and with hundreds of
>>threads active, it's quite common that you have lots of
>>very core data structures that might be touched by
>>multiple threads, but often are not in practice.
>>Things like locks for individual files or directories, or
>>a socket. Yeah, you may have multiple threads or processes
>>operating on them, but in 99% of all cases there is just a
>>single thread doing it - even when there are other threads
>>touching other files.
>>Some code goes to extreme extents to avoid the locking
>>costs, by turning it into a code size cost instead (ie
>>using conditional code to avoid the actual lock when you
>>know it's not needed). That doesn't always work (ie a lock
>>may not have any dynamic contention, but it could be
>>reached in theory, and has its own costs, obviously.
>So the question becomes, if you could design your own hardware based locking interface/functionality
>what would it look like? CMPXCHG? Some sort of advanced multiple LL/SC/transactional memory?

I like LL/SC not so much because of the slight advantage it has over cmpxchg in its semantics, but because the core can easily load the cacheline with write intent upon seeing an LL. Although I guess you can usually fit arbitrary operations between a regular load and the subsequent cas, so the LL/SC implementation might become LD; ...; LL; ...; SC;

I also like unconditional RMW instructions, like add, xchg and add-return, because then you aren't lumped with a branch (and presumably the optimal implementation of the simpler instructions can be made faster).

It would be nice to have a way around the lock instructions implying memory ordering that x86 has. I bet this was the biggest obstacle to making the instructions fast and pipelined. It also gives "too much" memory ordering on unlock instructions (when using non-trivial primitives like mutexes or reader/writer locks). Maybe Intel cores speculate around a lot of this, but still it would be nice to have a lock-weak prefix :) Maybe?

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