CMPXCHG latency

By: Zan (zan.delete@this.hate.spam.net), April 1, 2008 9:54 pm
Room: Moderated Discussions
>
>Why? Because I'm a big believer in OoO, I also think
>that being too low-level is actually bad for performance.
>I'd much rather take a "memset()" instruction and let
>the CPU do what's right for that cache and uarch than
>to have "nontemporal stores" and have software try to be
>clever. The same is true of locking.

You have lots of companies in believing the value OoO. Hopefully Intel won't drink the compiler kool-aid and goes down the path of lot of simple cores. Same can't be said in the value of software transparency. Ultimately uarch can only see a small windows of instructions and data access. To do what's right for that cache, CPU need some kind of sw hint - whether it's called "nontemporal stores" or not. Can't see how you can get around that. If anything, Intel should offer more explicit control over cache in their x86 line. Otherwise cell-like local cache implementations will eventually eat their lunch once the size constraint get lifted.



> ...
> I think you can get very very close with transactional
> memory, ...

Maybe you mean getting close in term of performance? There're a bunch of transaction memory papers claiming good performance. Upon careful examination, their good performance relied on either a) shooting against weak fine-grained locking implementations, b) cheating in the certification stage by hiding either the memory space cost or access cost of the log, usually both.

Many sw people shares your general dislike of TM. To be general purpose, TM hardware are going to have to keep track of all memory accesses happened up until the certification point, which is simply untenable in space/time cost when compared to judiciously placed locks. It's a dead end - promising in the beginning, but quickly get bogged down when pushed further.

ps. Haven't total understood you comment about pipelined atomic instructions. Any hw guys can shred some light on it? Thanks.
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