CMPXCHG latency

By: Zan (, April 2, 2008 12:11 am
Room: Moderated Discussions
Just caught a glimpse of what you are probably driving at. Given the common idioms in your example,

>list_add(entry, list);

What's needed from the atomic instruction in the spinlock() function is obviously some kind memory barrier semantics. In a safe but slow implementation you can flush all the pipelines and L/S buffers, then do a bus transaction to make sure you have local cache line in exclusive state. But in the uncontended common case, it's too wasteful for an OoO core.

Are you proposing to speculate past the atomic instruction and borrow a little bit from transaction memory? It's really plausible to speculate ahead and only abort when the local cache line which contains the atomic variable is not in exclusive state. If it can be done, it'll be a huge boost to lock performance in the common case.

Have you thought about bouncing your idea with Intel people. You guys are all in Hillsboro, right?
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