CMPXCHG - all or nothing

By: Linus Torvalds (, March 19, 2008 5:21 pm
Room: Moderated Discussions
Michael S ( on 3/19/08 wrote:
>According to my understanding, the main problem with x86
>synchronization primitives is that programmer is provided
>with either very lightweight or very heavyweight options
>when it would be nice to have something in the middle.

That's somewhat true.

I say "somewhat", because it's definitely the case that
the non-locking ones (which are only interrupt-safe, not
thread-safe) are really cheap, and the locking ones are
very expensive in comparison to the cheap ones.

BUT - and this is a big but - even the locking ones are
not actually really very expensive compared to many other
architectures doing the same things using other methods.

As already mentioned, LL/SC can be much more
expensive than a locked x86 instruction has ever been if
you just do it wrong, as it definitely has been done.

It all comes down to "implementation issue", and if there
is something that x86 shines at, it's all that engineering
that eventually gets done on all those implementation

>The heavyweight option (CMPXCHG with lock) guarantees
>both MP atomicity and "a total order" relatively to all
>other locked instructions, even at totally unrelated
>memory locations.

Yes and no.

It guarantees it from a software standpoint (the same
way Java guarantees a strongly ordered memory model), but
that by no means means that the hardware has to serialize
things completely.

Also, the x86 memory model is not a machine-wide
complete ordering - the memory model is called "processor
ordering", and it means that each CPU sees the stores of
other individual CPU's in a well-defined order.

See the Intel memory ordering whitepaper for all the gritty
details (just google for that phrase, the first hit will
be it).

>That's o.k. for 2-socket machine or for tightly-coupled
>4-socket, but I would imagine that on Altix-sized
>directory-based NUMA implementing the total order costs
>you more than microsecond. Or, may be, I overlooked some
>neat trick?

You overlooked two things, one trivial and one clever.

The trivial one is that the actual locked operations are
just done in the cache, and imply no actual barrier
semantics wrt other CPU's what-so-ever. They are only
serializing within that local CPU, and they absolutely
do not get more expensive with more CPU's.

(Of course, with lots of CPU's, it's more likely that you
will have cache contention on locks etc, and the cacheline
may be more likely to be on another CPU, so in that sense
it can and does get slower, but that's not an instruction
or ISA issue, that's just a generic property of any
shared access).

So the fact that a locked instruction is serializing only
matters for that one CPU - it does mean that the
trivial (stupid) solution is to make sure that the
instruction pipeline is flushed and all preceding writes
have moved from the write buffers into the cache.

This is why a locked instruction is pretty expensive on a
P4 (but still cheaper than LL/SC was on early alphas!): the
netburst architecture did that stupid thing with basically
a full pipeline flush and the pipelines were long.

But on many other x86 implementations a locked instruction
is literally just on the order of a couple of tens of
cycles, and the P4 really is the odd man out (not just in
this area - there's a lot of ops that it takes hundreds of
cycles at because it hits some random rough patch).

I think the AMD K8 does a locked cycle in 12 cycles in
many cases, for example, and while Core 2 takes more, it's
not orders of magnitude more, it's something like thirty
cycles, iirc. So we're still talking much much less than
a cache miss.

(Of course, locking does also get lots of cache
misses in many loads, but again, that's not an ISA issue,
that's just the nature of locking. There are other loads
where contention and cache misses almost never happen,
but you need to do the locking just because you have to
allow for the fact that they might happen).

However, the subtle thing you are missing is that even
that full pipeline flush is actually unnecessary. You only
need to serialize the pipeline if you can't keep track of
the ordering other ways than by just disabling everything
that might cause operations to reorder.

But if you are clever, what you do is to re-order
wildly all your operations as long as they hit in your
cache, and only care about being careful about the ordering
when it might be visible to other CPU's - when you have a
cache miss (or eviction due to a cache probe from outside).

So the x86 semantics are not actually horrible even now
(less so than others have done with "better" architectures)
and they can be made better. Which it sounds like Nehalem
is doing.

So in theory, a locked instruction should basically have
zero overhead over a non-locked one - but it does require
some more tracking resources to do that.

So to make an analogy: a conditional branch could cause
a full pipeline stall until the condition is resolved,
because the software-visible rules are that the branch
is "serializing" - you don't partially execute one side
until it's all been resolved, you do one side or the other,
very black-and-white.

But there are obviously ways to avoid that "serialization"
of the pipeline by using branch prediction, if you are just
willing to go to the effort of tracking which instructions
are done speculatively and can sort it out later if you were

The same is true of the strictly serializing software
semantics of a locked x86 instruction. You don't have
to stall the pipeline and serialize the memory queues. If
you're just willing and able to track the ordering of all
the memory accesses you do speculatively around the locked
instruction, and can sort it out later if you did them
in the wrong order.

In practice, nobody has ever done that for x86. Yet. Let's
see how close Nehalem gets.

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