CMPXCHG - all or nothing

By: Linus Torvalds (, March 21, 2008 8:47 am
Room: Moderated Discussions
Michael S ( on 3/21/08 wrote:
>>Why? Because processors 2 and 3 can only reorder their
>>reads to _x and _y if they keep them in their cache across
>>the execution of both instructions (otherwise, the load
>>reordering would be architecturally visible, which is
>>against 2.1).
>I disagree. The rule 2.1 insists on "program order". There
>is no particular program order between (xchg [ _x], ...)
>on Processor 0 and (xchg [ _y],...) on Processor 1.

Please read what I wrote.

I expressly talked about Processors 2 and 3. The ones that
do two loads.

Those loads are constrained to either have the two cache-
lines in the cache over both loads, or the second
load has to be loaded into the cache later. Otherwise you
would violate 2.1 on those CPU's.

It has absolutely nothing to do with the (single)
xchg on P0 and P1.

So the load reordering rules result in those two rules of

P2x -> P2y
P3x -> P3y

being a required ordering on those two CPU's. The argument
being that if you don't follow that simple rule, then you
are going to never be able to guarantee the load ordering
requirement of 2.1 without some magic external oracle (aka
complex global knowledge that is not appropriate for
the hottest path in the core!)

IOW, this is a practical rule, not a theoretical one. I'm
sure that in theory you could have some really
complex state machine with global knowledge, but I'm also
sure that in practice there is no way you can do that in
the memory pipeline any way close to reasonably.

>>So in order for the illegal case in 2.7 to happen (r3=1,
>>r4=0, r5=1, r6=0), we know that the movement for cacheline
>>_x must have been: P3x -> P0x -> P2x. And similarly for _y
>>it must have been P2y -> P1y ->P3y. Agreed?
>First, you assume a simple MESI or MESI-like implementation.

No, I do not.

I assume only cache coherency.

In order to do an atomic locked op, the CPU needs to hold
that cacheline exclusively in its cache. That is what I
assume, nothing more. It doesn't matter what the actual
implementation of the cache coherency protocol is.

>Second, even for MESI, in the initial state line _x could
>be shared between P0 and P3 or P0, P2 and P3. Same for
>line _y.

But that is irrelevant to my argument. Because of the locked
op, it will have to become unshared, and move to P0/P1 for
the duration of the locked op, and when it does so, it will
be exclusively at P0/P1.

In other words, the state before the xchg is irrelevant.

The only thing I'm saying is that the cachelines must
have moved like

P3x -> P0x -> P2x
P2y -> P1y -> P3y

where the middle case is exclusive. Yes, at the ends the
cacheline can also be shared with any number of
other CPU's, but that is not relevant to the argument. The
only part that is relevant is that at the points P0x and
P1y the cacheline cannot have been at any other CPU.

In other words, we knew the cacheline was at P3x (maybe
it was at some other place too but that doesn't
matter), and that it had to become exclusive at P0x, and
then went to P2x (and perhaps elsewhere).

We explicitly do not care about any "nonlocal"
information. The above looks only at two single cachelines
in individual CPU's, and looks at them as independent

So for example, P3x is literally "cacheline x in CPU3", it
does not imply that "cacheline x" might not exist
at any other CPU. But because of the values we see, we do
know that P3x (value=0) must have preceded P0x (xchange)
which must have preceded P2x (value=1) by only
depending on

- cache coherency
- causality

nothing else.

>>But now, look at P2: because of the load order requirement,
>>we know that P2 must have held _x before it held _y,
>>because otherwise the load ordering (rule 2.1) is no longer
>>valid. So we know that P2x -> P2y. Similarly, for the same
>>reasons, we know that P3y -> P3x.
>No. 2.1. load ordering applies only to locations modified
>by the same processor.

Again, irrelevant for my argument. You claimed that total
ordering was expensive. I showed that if you follow simple
rules, the total ordering is a local thing and not at all

And the simple rule (for loads) is:
- you can reorder loads arbitrarily as long as the
values loaded stay in the cache (no evictions) over
the whole sequence
- but if you don't have the values in cache, the cache
loads must be in program order.

Again, you seem to be arguing from some "unknown global
ordering" standpoint. I'm not. I'm arguing entirely from
the local ordering standpoint that gives you the semantics
that Intel guarantees.

So I'm arguing that in order for a CPU to honor the Intel
memory ordering rules, it can act the way I explained,
without any real "global state" (the cache coherency can
arguably be considered "global state", but I take that
one for granted - it's simply immaterial what the actual
cache coherency implementation is, as long as it gives
you coherency).

IOW, all the rules are local, and there is no extra cost
as the number of CPU's go up (again, apart from the cost
of cache coherency itself!).

Could you perhaps make up non-local rules that a CPU
designer could also use to implement the Intel
memory ordering rules? Oh, I'm sure you could. But since
that's the last thing you actually want to have, what's
the point?

I was describing the algorithm that I think Intel uses,
and gives the expected end results.

That said, I expressly avoided talking about the
problem cases. The real problem case is the write buffer
before a write actually hits the cacheline, but that was
not germane to this discussion, since the whole point was
about the nature of locked instructions which are in turn
guaranteed to act as if the buffer didn't exist (and
whether that is done by actually draining the buffer, or
by having strict rules about the elements in the buffer
having to already be backed by exclusive cache locations
or similar is then an implementation detail).

The write buffer itself doesn't participate in the cache
coherency, which is why loads can pass local writes etc.

And no, I will not guarantee that I got everything right.
But I think that you disagree with my analysis on the wrong
grounds: you seem to build your argument based on the
memory ordering whitepaper itself (and no assumptions about
how it's implemented), while I build my argument from the
standpoint of what I think the Intel implementation rules
are - and am trying to show that you can implement the
memory ordering without any nonlocal decisions.

IOW, I'm just arguing that the cost of a locked instruction
doesn't go up with number of CPU's, and it's actually
pretty cheap. It's pretty cheap even on current CPU's (which
all seem to basically drain the write queues and the
instruction pipeline - a few tens of cycles), but I think
it can be cheaper still if you use smarter models than a
full drain.

The expense in the Intel memory ordering model is:

- it likely needs bigger caches (and more ways) to work

Reason: the code can only do a good job of reordering
operations when they are in the cache, so if you want
the same amount of core freedom as with a more weakly
ordered model, you'd better make sure you don't have
unnecessary cache evictions.

So weakly ordered probably makes more sense if you have
a small one-way associative L1 cache. Of course, those
are horribly broken for other reasons, so..

- the write buffer is clearly much more complex, since it
requires that whole ordering thing (and again, reordering
is possible, but only if you can guarantee to keep
reordered accesses exclusively in the cache over the
whole reordered sequence - that way any other CPU is
guaranteed to not be able to see the reordered state!)

but a locked instruction - given the above caveats - is not
all that expensive on its own.

The write buffers are where I think all the real issues
are. They aren't cache-coherent, but they are on a really
critical path, and need to be coherent within the single
CPU. They also have these ordering guarantees (which can
be broken, but only if you maintain a few rules so that the
breakage isn't architecturally visible), along with the
whole synchronization thing too.

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