S. Rao (sonny@burdell.org) on 6/21/08 wrote:
---------------------------
>David Kanter (dkanter@realworldtech.com) on 6/21/08 wrote:
>---------------------------
>>someone (someone@somewhere.com) on 6/21/08 wrote:
>>---------------------------
>>>David Kanter (dkanter@realworldtech.com) on 6/21/08 wrote:
>>>---------------------------
>>>>x86
>>>>is vastly easier to multithread than IPF or RISCs in general.
>>>
>>>???
>>
>>Fewer registers to replicate. Nobody wants to have a 256 entry register file sitting
>>in a critical path...64 or 128 is much more manageable.
>>
>>DK
>
>(Maybe I'm way off here, but here goes)
>
>Remember that thing called register renaming ?
>
>Why does the architected register File have anything to
>do with it?

Doesn't matter whether you are accessing a true 256-entry architectural regfile or a 256-entry renamed regfile - either way you are accessing a lot of registers and so it is likely to become a significant timing path.

Furthermore, if you had an architectural regfile with 256-entries and decent compiler support you wouldn't need to do renaming. Power consumption wouldn't be nice though... nor would die area.

It also depends on your micro-architecture. If you are designing an OOO superscalar machine you will read the regfile contents into a reservation station which can decouple the timing paths.

The problem with an architectural regfile with a lot of entries comes when you want to push the architecture down into the low end space (in-order, possibly single issue), but maintain code compatability with the big processor. At this point a large architected regfile kills you.

Anyhow, apologies for the rambling.