unified physical register file nullifies x86 advantage

By: Michael S (already5chosen.delete@this.yahoo.com), June 22, 2008 12:24 am
Room: Moderated Discussions
Linus Torvalds (torvalds@linux-foundation.org) on 6/21/08 wrote:
---------------------------
>S. Rao (sonny@burdell.org) on 6/21/08 wrote:
>>
>>(Maybe I'm way off here, but here goes)
>>
>>Remember that thing called register renaming ?
>>
>>Why does the architected register File have anything to
>>do with it?
>
>You want to rename into a larger set of physical
>registers, not into a smaller one. The latter is possible
>but very very inconvenient (it is what you effectively
>have to do if you are emulating a large register file
>architecture on a CPU with a smaller register file: you
>map the large register file into cache or some other
>"secondary" register file, and then rename it all into the
>smaller actual register file).
>
>So even with renaming, you do care about the size of the
>architected register file. A smaller architected register
>file allows you more flexibility in choosing the size of
>the actual hardware register file.
>
>Linus

Doesn't Intel Merom line have unified physical register file for GP, x87/MMX and XMM registers?
If it does then they have 40 "architected" registers per thread per regfile - 8 more than IBM power4/5 that IFAIR keeps separate register files for GP and FP registers and has no Altivec registers at all.

P.S.
I checked in Intel optimization guide. MOVD instruction that transfers data between GP and XMM registers has the latency of 1 clock and the throughput of 2/clock.
For comparison, on AMD Greyhound that is known to have separate GP and FP/XMM register files the latency of MOVD= 3 or 6 clocks depending on direction of transfer and the throughput = 1/clock.
In light of these numbers I am sure that Intel Merom processors (as well as PM/Yonah) have unified physical register file.
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