unified physical register file nullifies x86 advantage

By: David Kanter (dkanter.delete@this.realworldtech.com), June 22, 2008 9:35 am
Room: Moderated Discussions
Michael S (already5chosen@yahoo.com) on 6/22/08 wrote:

>Doesn't Intel Merom line have unified physical register file for GP, x87/MMX and XMM registers?
>If it does then they have 40 "architected" registers per thread per regfile - 8
>more than IBM power4/5 that IFAIR keeps separate register files for GP and FP registers
>and has no Altivec registers at all.

So I'm not sure what the PPC reg files look like. There's going to be 32 integer, 8 cc registers, 32 fp registers and probably some registers for altivec, right?

DK
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