Michael S (already5chosen@yahoo.com) on 6/22/08 wrote:

>Doesn't Intel Merom line have unified physical register file for GP, x87/MMX and XMM registers?
>If it does then they have 40 "architected" registers per thread per regfile - 8
>more than IBM power4/5 that IFAIR keeps separate register files for GP and FP registers
>and has no Altivec registers at all.

Also, the reason that the P6 has a big register file is that the register file is rarely used an operand source. I've talked a bit with Andy Glew about this, and he's pretty insistent that in a P6-style microarchitecture, the vast majority of your input operands come from the forwarding network, rather than the physical register file itself.

I'm not sure if that's true of a P4 or K8 style microarchitecture. I believe the POWER4/5 is closest to the K8 from a microarchitectural perspective. I'm not quite sure how to classify the POWER6 yet...

I also don't recall the microarchitecture for OOO that the EV8 was going to use. I definitely recall it being unified and more sensible than the EV6/7, which used more CAMs than it needed to.

DK