Reg file vs. forwarding network

By: Anders Jensen (.delete@this..), June 23, 2008 11:05 am
Room: Moderated Discussions
hobold (hobold@informatik.uni-bremen.de) on 6/22/08 wrote:
---------------------------
>David Kanter (dkanter@realworldtech.com) on 6/22/08 wrote:
>---------------------------
>[...]
>>Also, the reason that the P6 has a big register file is that the register file
>>is rarely used an operand source. I've talked a bit with Andy Glew about this,
>>and he's pretty insistent that in a P6-style microarchitecture, the vast majority
>>of your input operands come from the forwarding network, rather than the >physical register file itself.
>>
>This is correct, the P6 microarchitecture is optimized for execution of serially
>dependent instructions. The designers managed to convert the weakness of the small
>'x86 architected register file (which resulted in lots of (false) dependencies in
>most code) into a strength of the implementation.
>
>Other architectures which aimed to express more parallelism in their ISA (not just
>EPIC, also RISCs with their large register files and three operand encoding) were not as lucky in realizing a benefit.

The problem with evaluating CPU architecture today is that we are most likely at a extreme in the history of uarch optimization now with current software base being more dependent on single threaded performance than ever. Of course new software tends to be multi threaded to a higher degree so over time this focus will change and CPU architecture will change with it. Add the power efficiency focus to this and it is very obvious that future architectures will have very different optimization than, say Nehalem, which is now coming out with 36 reservation stations. A record that hopefully will never be beaten. IMO doing as good as possible with in-order pipeline is what will be important going forward. In-order can get vastly more throughput than OoOE can dream of, but Amdahls law is going to be a big problem so whoever gets most performance per thread has a big advantage.

I think x86 is going to get major problems here. Reservation stations and register renaming is bad for throughput/watt.

>I sometimes wonder if we should not experiment more with ISAs that make dependencies
>explicit rather than parallelism. I am aware of only a single old academic project
>named "WM - Weird Machine". It encoded instructions as dependent pairs with implicit
>producer/consumer dataflow. You could say it generalized things like 'fused multiply
>add', or the complex 'load effective address' instructions.

Check out TRIPS.
http://en.wikipedia.org/wiki/TRIPS_architecture
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