Reg file vs. forwarding network

By: left nutz (sorry.delete@this.none.available.com.invalid), June 27, 2008 7:31 am
Room: Moderated Discussions
hobold (hobold@informatik.uni-bremen.de) on 6/22/08 wrote:
---------------------------
[scissors]
>I sometimes wonder if we should not experiment more with ISAs that make dependencies
>explicit rather than parallelism. I am aware of only a single old academic project
>named "WM - Weird Machine". It encoded instructions as dependent pairs with implicit
>producer/consumer dataflow. You could say it generalized things like 'fused multiply
>add', or the complex 'load effective address' instructions.

You may want to look up a research architecture called TRIPS. Far as I remember it was supposed to be a 4x4 grid of ALUs with load/store/register units at the edges, the instruction format being a sort of a texan vision of VLIW with essentially everything that goes between non-predicate-transformable branches in one xbox-hueg packet. Instead of registers, the instructions specified the operation to perform once all inputs are available and _routing_ for the output(s).

The central advantage was supposed to be relieving pressure from the register file, besides the potential for quite a bit of ILP assuming availability of data (which I think they were supposed to solve with SMT, quite a tall order there). And most of the bad bits about VLIW (with the exception of too many NOPs taking up space) would still be present.

Also I bet they'd have some right royal pain with being future-compatible.
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