SSE5 has a great chance for fiasco

By: Agner (www.agner.org.delete@this.nospam.no), June 22, 2008 3:32 am
Room: Moderated Discussions
My point was that AMD SSE5 and Intel AVX have two different ways of coding instructions with 3 or 4 operands. AMD have to support the AVX encoding because it is more efficient and flexible and because it is needed for future extensions that AMD cannot afford to ignore. Intel is certainly not going to copy SSE5 when they have something better. Having two different coding schemes makes the instruction decoder more expensive.

The best thing AMD can do now is to replace SSE5 by something completely different - and still call it SSE5. From a marketing point of view it is better to say we have revised SSE5 due to public demand than to say we have dropped SSE5 because Intel had something better.

AMD should modify SSE5 instructions to make them compatible with similar Intel instructions as far as possible, and make the rest of the instructions compatible with the AVX coding scheme and with future extensions of the register size.
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      So...Dean Kent2008/06/22 07:35 AM
  SSE5 has a great chance to succeed.mpx2008/06/22 12:25 AM
    SSE5 has a great chance to succeed.Michael S2008/06/22 01:42 AM
      SSE5 has a great chance for fiascoAgner2008/06/22 03:32 AM
        SSE5 has a great chance for fiascoIan Ameline2008/06/22 08:37 AM
        SSE5 has a great chance for fiascoanonymous2008/06/22 09:02 AM
          SSE5 has a great chance for fiascohobold2008/06/22 12:59 PM
            SSE5 has a great chance for fiascoHoward Chu2008/06/22 04:38 PM
      SSE5 has a great chance to succeed.hobold2008/06/22 12:52 PM
        SSE5 has a great chance to succeed.Michael S2008/06/22 01:46 PM
          SSE5 has a great chance to succeed.Hannes2008/06/24 08:49 AM
            SSE5 has a great chance to succeed.anonymous2008/06/24 10:46 AM
          SSE5 has a great chance to succeed.Ian Ollmann2008/06/24 10:12 PM
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