By: David Kanter (dkanter.delete@this.realworldtech.com), October 31, 2008 8:38 am
Room: Moderated Discussions
Michael S (already5chosen@yahoo.com) on 10/30/08 wrote:
>
>O.k. Then more nitpicks:
>
>Chart 2 – System Settings/System Bus you use clock frequency for AMD vs transfer rate for Intel. That's inconsistent.
>It would be better to mention either clock rate vs clock rate, i.e. 1000 MHz vs
>266 MHz or transfer rate vs. transfer rate, i.e. 2000 MT/s vs 1066MT/s.
That's a good point, as soon as I get my PC up and running, I'll try and fix that.
>Also in the same chart you mention nForce 590 SLI as a Northbridge. I'd >rather
>say that the on AMD platform the Northbridge is integrated. nForce chip >better fits thd Southbridge moniker.
Fair enough.
>Same page, Figure 1:
>Merom
>6MB L2 is Penryn, not Merom that you tested.
Whoops, yet another mea culpa.
>Execution port 0 can't do SSE Shuffles.
>
>Execution port 1 can't do SSE MUL, it can do FP/SSE MOVE and Logic + 64-bit fixpoint
>shuffle (or 128bit fixpoint shuffle at reduced performance).
>
>Execution port 2 does complete Integer/FP load, not just Load Address. Memory data
>arrives to the inner core through writeback port 2.
Let me take a look at these a bit more.
>K8:
>Unlike Intel where all external memory/IO accesses travel through L2 cache, > on
>K8's SRQ is actually attached directly to all three caches.
>
>IMHO, you should draw L1 TLBs on the right (system) side of respective data >caches.
>This way you make clear that AMD L1 caches while physically-tagged are >virtually-indexed.
>AMD itself certainly draws L1 TLBs on the system side.
Good point.
>The arrows between the L1D and LSU_1 create an impression that LSUs are >fully symmetric
>and can sustain any combination of loads and stores. That's incorrect. K8 >L1D cache
>could sustain at most one store per clock.
I believe when I characterized it in the barcelona article, I made it clear that stores all go through the 2nd LSU, but that text is no longer attached to the diagram.
David
>
>O.k. Then more nitpicks:
>
>Chart 2 – System Settings/System Bus you use clock frequency for AMD vs transfer rate for Intel. That's inconsistent.
>It would be better to mention either clock rate vs clock rate, i.e. 1000 MHz vs
>266 MHz or transfer rate vs. transfer rate, i.e. 2000 MT/s vs 1066MT/s.
That's a good point, as soon as I get my PC up and running, I'll try and fix that.
>Also in the same chart you mention nForce 590 SLI as a Northbridge. I'd >rather
>say that the on AMD platform the Northbridge is integrated. nForce chip >better fits thd Southbridge moniker.
Fair enough.
>Same page, Figure 1:
>Merom
>6MB L2 is Penryn, not Merom that you tested.
Whoops, yet another mea culpa.
>Execution port 0 can't do SSE Shuffles.
>
>Execution port 1 can't do SSE MUL, it can do FP/SSE MOVE and Logic + 64-bit fixpoint
>shuffle (or 128bit fixpoint shuffle at reduced performance).
>
>Execution port 2 does complete Integer/FP load, not just Load Address. Memory data
>arrives to the inner core through writeback port 2.
Let me take a look at these a bit more.
>K8:
>Unlike Intel where all external memory/IO accesses travel through L2 cache, > on
>K8's SRQ is actually attached directly to all three caches.
>
>IMHO, you should draw L1 TLBs on the right (system) side of respective data >caches.
>This way you make clear that AMD L1 caches while physically-tagged are >virtually-indexed.
>AMD itself certainly draws L1 TLBs on the system side.
Good point.
>The arrows between the L1D and LSU_1 create an impression that LSUs are >fully symmetric
>and can sustain any combination of loads and stores. That's incorrect. K8 >L1D cache
>could sustain at most one store per clock.
I believe when I characterized it in the barcelona article, I made it clear that stores all go through the 2nd LSU, but that text is no longer attached to the diagram.
David
