slacker (s@lack.er) on 2/6/09 wrote:
>
>You might want to note that QPI was implemented at the 65nm
>node for Tukwila, and 45nm for Nehalem. Maybe you can call
>your friends at Transmeta Novafora and ask them
>how easy it is to synthesize high-speed I/O cells from
>Verilog. Prepare for laughter.

.. I bet the much bigger headache is the protocol design
and verification. Yes, yes, you will want to also have a
damn good set of people for the actual IO cells, but which
part do you think a CPU architect really worries about:
the cache coherency protocol and logic verification, or
the low-level IO?

I know which one I'd worry about, and which part would
keep me up at night. Especially considering how Intel has
lots of good people to do the actual low-level stuff (ie
it was never a question of "we don't have that kind of
expertise in-house and it's something new to us").

So no, you wouldn't move the thing untouched, but the parts
that really matter should all translate beautifully from
45nm to 65nm, and is at a much higher level. Don't tell me
that Itanium QPI couldn't leverage 90% of the work from
the fact that x86 did it.

In fact, even if you never lifted a single line of verilog
(which I doubt is the case), just the test infrastructure
and the verification of the protocol itself is a huge deal.

Don't you agree?

Linus