Article on 32nm process tech from IEDM 08 and VLSI 09 online

Article: Process Technology at IEDM 2008
By: Hans de Vries (spam.delete@this.send2nowhere.com), August 4, 2009 11:56 am
Room: Moderated Discussions
David Kanter (dkanter@realworldtech.com) on 8/3/09 wrote:
---------------------------
>Hans de Vries (spam@send2nowhere.com) on 8/3/09 wrote:
>---------------------------
>>David Kanter (dkanter@realworldtech.com) on 8/3/09 wrote:
>>---------------------------
>>>Hans de Vries (all@spam2nowhere.com) on 8/3/09 wrote:
>>>---------------------------
>>>>Good job David
>>>>
>>>>Regards, Hans
>>>
>>>Thanks Hans!
>>>
>>>David
>>>
>>
>>Hi, David
>>
>>You might like to read the presentations here about the
>>road(s) to 22nm, from Intel, IBM, GlobalFoundries ...
>>
>>http://www.semiconwest.org/ProgramsandEvents/Techxpots/ctr_029497?linkval=Device%20Scaling&parent=yes&parentId=5
>>
>>The numbers claimed by a poster for TSMC's 28nm process
>>are 1360/960 ua/um (see the comment section here:)
>>http://www.electronicsweekly.com/blogs/david-manners-semiconductor-blog/2009/04/tsmc-to-beat-intel-and-globalf.html
>>
>>>
>
>Very interesting. Thanks for the link....I'll try and update my table.
>
>>Intel doesn't use Double Patterning for 65nm, 45nm and
>>32nm as far as I know. Information about this can be
>>found in this Intel presentation:
>
>If you read the presentation carefully, you'll see the two views aren't mutually exclusive.
>
>I've been told directly by Mark Bohr that they are using double patterning, and
>if you look at the SRAMs, it is not possible to achieve smooth and well defined
>end caps without DP. I've talked with one academic who was pretty clear on the matter.
>
>If you look at what he said in his presentation - most layers are not using DP. But some layers are.
>
>DK

I see what you mean from slacker's link. You can indeed
call this Double Patterning, although it increases fidelity
rather than resolution. In this case the quality of the
end caps.

What I had in mind, and Yan Borodovsky also, is what is
more accurately described by the term "Pitch doubling"
That is, multiple exposures are used to increase the
line density (= to decrease the line pitch) in order
to create a line pattern which is up to twice as dense.

To do so requires Lithography tools with an overlay
accuracy of ~3nm for the 32nm process node and the
tools Intel uses from Nikon (the C610) have an overlay
accuracy specified as <6.5nm

This is the main reason that IBM and TSMC who use the
ASML XT:1950Hi with an overlay accuracy of <4nm have
somewhat smaller SRAM cells and presumably somewhat
higher logic densities.

With all the tricks one can invent it is ultimately the
Lithography equipment which determines how far you
can go.

The main race in Immersion Lithography going on is to
increase (double) the wafers per hour and to triple
the overlay accuracy (to 2nm) for the 28nm process
node using Double Pattering to reduce the line pitches.


Regards, Hans


< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Article on 32nm process tech from IEDM 08 and VLSI 09 onlineDavid Kanter2009/08/03 01:22 AM
  Article on 32nm process tech from IEDM 08 and VLSI 09 onlineHans de Vries2009/08/03 02:28 AM
    Article on 32nm process tech from IEDM 08 and VLSI 09 onlineDavid Kanter2009/08/03 02:47 PM
      Article on 32nm process tech from IEDM 08 and VLSI 09 onlineHans de Vries2009/08/03 04:51 PM
        Article on 32nm process tech from IEDM 08 and VLSI 09 onlineDavid Kanter2009/08/03 10:09 PM
          Article on 32nm process tech from IEDM 08 and VLSI 09 onlineHans de Vries2009/08/04 11:56 AM
            Article on 32nm process tech from IEDM 08 and VLSI 09 onlineHans de Vries2009/08/04 12:31 PM
        Article on 32nm process tech from IEDM 08 and VLSI 09 onlineslacker2009/08/04 10:37 AM
          Article on 32nm process tech from IEDM 08 and VLSI 09 onlineAlexander Tomkins2009/08/04 11:36 AM
            Article on 32nm process tech from IEDM 08 and VLSI 09 onlineslacker2009/08/04 03:10 PM
              Article on 32nm process tech from IEDM 08 and VLSI 09 onlineAlexander Tomkins2009/08/04 07:12 PM
        Thanks for spotting thatDavid Kanter2009/08/05 01:30 AM
  Article on 32nm process tech from IEDM 08 and VLSI 09 onlinea reader2009/08/03 09:57 AM
    Article on 32nm process tech from IEDM 08 and VLSI 09 onlineAlexander Tomkins2009/08/04 11:30 AM
    smaller but better I_on/I_offMoritz2009/08/09 03:20 AM
      smaller but better I_on/I_offDavid Kanter2009/08/09 10:15 AM
  Article on 32nm process tech from IEDM 08 and VLSI 09 onlineWilliam Campbell2009/08/03 05:37 PM
  Article on 32nm process tech from IEDM 08 and VLSI 09 onlineBryan Catanzaro2009/08/04 07:04 AM
  Intel 32 nm PMOSjokerman2009/08/04 12:09 PM
    Intel 32 nm PMOSDavid Kanter2009/08/04 12:57 PM
    Good eyeDavid Kanter2009/08/05 01:30 AM
  TSMC 28nm: major changes?One Anonymous2009/08/05 01:31 AM
    TSMC 28nm: major changes?David Kanter2009/08/05 02:34 AM
      TSMC 28nm: major changes?anon2009/08/05 08:20 AM
        TSMC 28nm: major changes?David Kanter2009/08/05 12:04 PM
  Article on 32nm process tech from IEDM 08 and VLSI 09 onlineanon2009/08/07 01:48 PM
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