Article on 32nm process tech from IEDM 08 and VLSI 09 online

Article: Process Technology at IEDM 2008
By: slacker (s.delete@this.lcak.er), August 4, 2009 10:37 am
Room: Moderated Discussions
Hans de Vries (spam@send2nowhere.com) on 8/3/09 wrote:
---------------------------
>Intel doesn't use Double Patterning for 65nm, 45nm and
>32nm as far as I know. Information about this can be
>found in this Intel presentation:
>
>Borodovsky, Yan. Marching to the Beat of Moore's Law.
>Proceedings of SPIE—Volume 6153, Advances in Resist
>Technology and Processing XXIII, March 2006.

I read this last month:

"Intel's 45nm CMOS Technology
June 17, 2008

The gate patterning process uses a double patterning scheme. Initially the gate stack is deposited including the polysilicon and hardmask deposition. The first lithography step patterns a series of parallel, continuous lines. Only discrete pitches are allowed, with the smallest at 160nm, to assist in the patterning. A second masking step is then used to define the cuts in the lines. The two-step process enables abrupt poly endcap regions, devoid of rounding that allows for tight contact-to-gate design rules"

http://www.intel.com/technology/itj/2008/v12i2/1-transistors/4-designrules.htm
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TopicPosted ByDate
Article on 32nm process tech from IEDM 08 and VLSI 09 onlineDavid Kanter2009/08/03 01:22 AM
  Article on 32nm process tech from IEDM 08 and VLSI 09 onlineHans de Vries2009/08/03 02:28 AM
    Article on 32nm process tech from IEDM 08 and VLSI 09 onlineDavid Kanter2009/08/03 02:47 PM
      Article on 32nm process tech from IEDM 08 and VLSI 09 onlineHans de Vries2009/08/03 04:51 PM
        Article on 32nm process tech from IEDM 08 and VLSI 09 onlineDavid Kanter2009/08/03 10:09 PM
          Article on 32nm process tech from IEDM 08 and VLSI 09 onlineHans de Vries2009/08/04 11:56 AM
            Article on 32nm process tech from IEDM 08 and VLSI 09 onlineHans de Vries2009/08/04 12:31 PM
        Article on 32nm process tech from IEDM 08 and VLSI 09 onlineslacker2009/08/04 10:37 AM
          Article on 32nm process tech from IEDM 08 and VLSI 09 onlineAlexander Tomkins2009/08/04 11:36 AM
            Article on 32nm process tech from IEDM 08 and VLSI 09 onlineslacker2009/08/04 03:10 PM
              Article on 32nm process tech from IEDM 08 and VLSI 09 onlineAlexander Tomkins2009/08/04 07:12 PM
        Thanks for spotting thatDavid Kanter2009/08/05 01:30 AM
  Article on 32nm process tech from IEDM 08 and VLSI 09 onlinea reader2009/08/03 09:57 AM
    Article on 32nm process tech from IEDM 08 and VLSI 09 onlineAlexander Tomkins2009/08/04 11:30 AM
    smaller but better I_on/I_offMoritz2009/08/09 03:20 AM
      smaller but better I_on/I_offDavid Kanter2009/08/09 10:15 AM
  Article on 32nm process tech from IEDM 08 and VLSI 09 onlineWilliam Campbell2009/08/03 05:37 PM
  Article on 32nm process tech from IEDM 08 and VLSI 09 onlineBryan Catanzaro2009/08/04 07:04 AM
  Intel 32 nm PMOSjokerman2009/08/04 12:09 PM
    Intel 32 nm PMOSDavid Kanter2009/08/04 12:57 PM
    Good eyeDavid Kanter2009/08/05 01:30 AM
  TSMC 28nm: major changes?One Anonymous2009/08/05 01:31 AM
    TSMC 28nm: major changes?David Kanter2009/08/05 02:34 AM
      TSMC 28nm: major changes?anon2009/08/05 08:20 AM
        TSMC 28nm: major changes?David Kanter2009/08/05 12:04 PM
  Article on 32nm process tech from IEDM 08 and VLSI 09 onlineanon2009/08/07 01:48 PM
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