anon (no@no.no) on 8/14/09 wrote:
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>Gabriele Svelto (gabriele.svelto@gmail.com) on 8/14/09 wrote:
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>>anon (no@no.no) on 8/13/09 wrote:
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>>>A bit off-topic, but I wonder how high Intel would be able to clock Netburst if
>>>they had just kept shrinking it and improving it where necessary (IMC, better SIMD,
>>>etc). The last 65nm dual-core P4 had 3.6GHz and TDP 95W, and looking around it seems
>>>that overclocks to 4.4GHz were common.
>>
>>The latest stepping of 65nm P4 did have a 65W TDP actually and very low idle power.
>>Compared to the previous rounds of Prescotts they were decent desktop processors, but still not as good as the C2Ds.
>
>65W for single-core and 95W for dual-core, IIRC.

That's without any of the features that'd need to be added to allow it to compete with a modern Nehalem.

>>>I guess that a 32nm "P4" would reach 6.x GHz?
>>
>>Some people actually hit 8 Ghz with insance voltage and cooling proving that the
>>microarchitecture was designed with a significantly higher frequency target compared
>>to what did actually get on our desks. Though the performance benefits of such high
>>clocks are doubtful. As others pointed out K8 and C2D proved that IMCs, shorter
>>pipelines and seas of low-latency caches would be a much better road to follow.
>
>But couldn't IMC, better caches, better SIMD and other enhancements also be done to Netburst?
>I don't deny the merits of Core2 and i7 and I'm not really defending the P4, but
>if one says that i7 has 2x the IPC of Netburst but Netburst can have 2x the clock,
>then it seems that Intel could have kept improving netburst similarly to what AMD
>did to K7/K8/K10 if they really wanted.

Possibly. But that particular architecture and its design philosophy did not mix well with modern power-saving features. When you have a long but narrow pipeline, every part of the chip has to switch. In a short-but-wide pipeline, if you're only processing half the amount of data, you can shut off the other half of the pipeline.

Then there's the fact that the higher your frequency requirement, the less margin you have for things like undervolting (dynamic voltage scaling), dynamic underclocking (accuracy vs speed is a very real PLL trade-off), IDDQ (you can't afford too much on-chip supply drop with every part being high-speed) and the very fact that switching and leakage power grows non-linearly with faster transistors.

It could've been improved, but not to the degree that the current C2D derivatives could; not without a much higher power envelope.