mpx (mpx@nomail.pl) on 8/25/09 wrote:
---------------------------
[..]
>Now, with enough time to
>spend on Power7 architecture they are back with a superior design.

Technical tidbits disclosed so far are intriguing
but that statement clearly remains to be seen.

In the prelease hype before Power6 some folks who
should have known better got caught up in high GHz
fever and forgot that there would have to be design
tradeoffs that IBM would go far out of its way not
to mention. Heck, IBM still won't even hang a TDP
number on it. Power6 turned out to be remarkably
inefficient in its ability to turn frequency, issue width,
and bandwidth into application level performance.

Doubling core count and bringing on-board the L3
means compromises in the area and thermal budgets
per core. What those are will have to be teased out
of ISSCC papers and JSSC articles over the next 6
to 12 months.

At Hotchips we will hear all about the sizzle of the
Power7 steak as IBM's customary trade press hype
gets turned up to 11 but it will be only after Power7
gets in the hands of customers we will find out its
true cholesterol content. :-)