David Kanter (dkanter@realworldtech.com) on 8/28/09 wrote:
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>someone (someone@somewhere.com) on 8/28/09 wrote:
>---------------------------
>>David Kanter (dkanter@realworldtech.com) on 8/28/09 wrote:
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>>[..]
>>>That does not necessarily explain the choice of atom. What if the primary issue
>>>was time to market, and it was judged to be easier to recycle the P5 than to design a new uarch from scratch?
>>
>>The P5 and Atom share two common attributes, both are
>>dual issue, and both are in-order. Other than that they are
>>*very* different animals.
>
>The cores are similar enough. Adding SMT was a non-trivial control change, and
>the cache hierarchy has changed a bit, but it still looks like about the same core uarch to me.

LOL, the P5 has a 5 stage pipeline while Atom has a 16
stage pipeline. The P5 can do two load accesses per
cycle, the Atom can only do one. The P5 can only do one
FP compute instruction per cycle, Atom do an FADD and
an FMUL in the same cycle.

Like I said before, the P5 and Atom share two common
attributes, both are dual issue and both are in-order but
other than that they are *very* different animals.