Jouni Osmala (josmala@cc.hut.fi) on 9/2/09 wrote:
---------------------------
>>>OoO means more work in the earlier stages of pipeline, AND longer critical path from instruction fetch to execute.
>>>Now you have couple of choices.
>>>
>>>A) Increase pipeline length.
>>>B) Reduce clock speed.
>>>C) Improve enough some delay to compensate the extrawork, and EV6 did that by redesigning
>>>the clockdistribution system. However, with equal clock generation hardware inorder system would clock higher.
>>
>>More work (+ die space) -- yes, indeed, but the last statement is not obvious at all. Why?
>
>If clockcycletime = Work+latch_delay+sometime required to handle variations in clock distribution network.
>IF B) Happens instead of A) in design, and it has SOME headroom to improve latchdelay
>or clockdistribution variation then, it to keep clockcycle time could stay still
>while doing longer delay of work in the stage by improving the latch and clocking
>network. Like happened with EV6 but to a more serious issue is that its too slow.
>
>>Which part of OoO stuff imposes a hard limitation on clock rate, hittable by an
>>in-order chip, yet unhittabble by an ooo chip?
>
>I doubt that I would be qualified to answer that.
>I personally think that OoO:s main limitations are extra power and that it increases
>the length of pipeline IF all other parameters would be equal.

Power and space yes, the question is by how much. E.g. PPC750 and esp. 603 consumed only a few watts and had a very modest non-cache transistor count by any standards. What do you think power and pipeline-length overheads are there due to ooo?

As for pipeline length, quickly checking, PPC 604e had 6-stage pipeline (fetch, decode, dispatch, execute, complete, writeback), and PPC750 outdid 604e with 4 stages, apparently combining decode+dispatch and complete+writeback; consumed a few watts and ISSCC presentation reports 500 MHz in 0.2um process: http://isscc.org/isscc/1998/ap/FP15.htm What is the impact of OoO on the length of the pipeline?

In case you don't like old slow chips, let's take Netburst. Power efficiency is not its hallmark, but still how much do you think it lost in clock rate due to being an OoO design?

I'll think that most
>of the time it just couple of extra stages in pipeline and keep the clockspeed same
>as would be inorder design, and pay it by extra power consumption and extra die size.
>(which in inorder design could have been dedicated to extra function units or extra
>cores, or just saved for battery life)
>
>>Any good examples? Or is that from your own design experience?
>
>Some is from theoretical designs done while studying, but the choice C is much
>directly from a course in which lecturer disected the EV6->EV5 transition electrical
>design changes in detail to PHD students over several lectures.

Circuit design could have improved, but it couldn't have delivered a massive improvement (so EV6-style EV5 would clock say, 1.5x faster), no frigging way. What are your (your lecturer's) estimations on how much EV6 gained due to circuits and how much it lost back from OoO?