>>I doubt that I would be qualified to answer that.
>>I personally think that OoO:s main limitations are extra power and that it increases
>>the length of pipeline IF all other parameters would be equal.
>
>Power and space yes, the question is by how much. E.g. PPC750 and esp. 603 consumed
>only a few watts and had a very modest non-cache transistor count by any standards.
>What do you think power and pipeline-length overheads are there due to ooo?

And both clocked for lower than other chips made in the same process tech...

>As for pipeline length, quickly checking, PPC 604e had 6-stage pipeline (fetch, decode, dispatch, execute, complete, writeback), and PPC750 outdid 604e with 4 stages, apparently combining decode+dispatch and complete+writeback; consumed a few watts and ISSCC presentation reports 500 MHz in 0.2um process: http://isscc.org/isscc/1998/ap/FP15.htm
>What is the impact of OoO on the length of the pipeline?
>
>In case you don't like old slow chips, let's take Netburst. Power efficiency is
>not its hallmark, but still how much do you think it lost in clock rate due to being an OoO design?

I think what I'm all going to reiterate, Everything is a trade-off. Power-efficiency vs clockspeed is a trade off.
Pipeline length vs clockspeed on given process is a tradeoff. Now OoO logic costs some of that TOTAL to be traded between other variables. And better implementation techniques give that total, and for better or worse, only people capable of estimating that well are the people who made the original design for each design. Software people are as good estimating hardware design trade offs as economists are estimating software design decisions.
And what worst, the thing that we see it takes lots of research to find other components of the trade offs and we most likely never get most of them.
OoO logic costs. It costs as much power as FPU and integer pipelines combined, for EV6 example.
Which isn't huge percentage but if we take away first percentage of clock since that is somewhat dependent on how much other things are going on chip and then count its percentage from the rest of the thing its about third of peak power consumption.

Sure you CAN do either 600W 6Ghz OoO chip, or 1Ghz low power OoO chip, or Equal charasteristics inorder chip.
The 1Ghz version is going to have shorter pipeline than 6Ghz version, UNLESS they use the long pipeline to scale down supply voltage, which is another possible trade off.
I'd say without being OoO last P4 would have gotten the clockspeed it was designed for, instead of hampered by power consumption. I think designing such CPU would be waste of time though. x86 :s advantage is ability to run legacy x86 software faster than inside emulator on other architectures and OoO is good for legacy software support.

>>directly from a course in which lecturer disected the EV6->EV5 transition electrical
>>design changes in detail to PHD students over several lectures.
>
>Circuit design could have improved, but it couldn't have delivered a massive improvement
>(so EV6-style EV5 would clock say, 1.5x faster), no frigging way. What are your
>(your lecturer's) estimations on how much EV6 gained due to circuits and how much it lost back from OoO?

Well It was old. But lets put it this way I couldn't find anywhere any other mention about than both more aggressive implementation techniques was used with EV6 than before.
Anyway those lectures where LONG time ago...