>>EV6@EV5 had different pipeline length atleast from fetch to execute. EV5 started
>>execute in stage S4 and EV6 in stage S5, also EV5 has extra stages that are not
>>necessarily required in simple inorder pipeline, but are beneficial.
>>First is buffer stage, which basicly separates execution from instruction fetch,
>>just like issue buffer in OoO chips but is fully inorder.
>>And slotting stage which is not required if A) each pipeline could execute any instruction, B) in VLIW design.
>>So from EV5->EV6 transition I can argue that OoO lengthens the pipeline by stage or 3.
>>I didn't check your assumptions on their pipeline lengths until now when I was
>>wondering why EV5 would have such a long pipeline, and answer was that it didn't
>>it was 1 cycle shorter than EV6 pipeline.
>
>There were no assumptions and sorry, I don't get your logic at all. Maybe you mix
>up, say, misprediction penalty (which can indeed be different) with pipeline length?
>The pipelines are rather different acc. to DEC's papers, yes, but the length is clearly stated to be 7 stages in both.

I look what each pipeline stage DOES, and EV6:s SINGLE exec stage does what EV5 first exec stage does, and EV5 second exec stage functionality takes two more cycles than whats shown in the simplified pipeline of EV6. And by comparing the from fetch-> end of THOSE instructions is even worse for EV6...

In EV6 pipeline doesn't include L1 data cache latency, while EV5 pipeline includes L1 data cache latency as part of measurement of pipeline length. So its apples to oranges comparison, see number of execution stages in either pipeline BOTH have 1 cycle and multicycle instructions, both pipelined, however EV6 diagram just don't show the multicycle instruction pipeline while EV5 does. But most relevant way of counting pipeline length is from Fetch to integer ALU result, which was done on EV6 pipeline, EV5 pipeline had L1 memory stage included AFTER the exec stage that was equal to EV6 exec stage.

IF EV6 pipeline would of counted the same way as EV5 pipeline it would be 9 stage pipeline, due to fact that what EV5 did in 2nd execution stage, took EV6 a cycle more than in EV5 and it was omitted from EV6 pipeline diagram.

What MY original claim was that OoO logic takes extra stage(s) between fetch and execute and THAT gives extra branch misprediction penalty, and that is THE extra cost for OoO execution besides the power and area costs.
If you go read what each pipeline stage DOES then you understand that yes, there is logical reason why EV6 has another pipeline stage,

I cut most of discussion to make my point simpler for you to understand by just keeping it on single simplest example