(I tried to post this message before but it seems I didn't succeed. If this is a double post, sorry about that.)

Seni (seniike@hotmail.com) on 9/26/09 wrote:
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>>1) Out-of-order adds more transistors[1]
>>2) More transistors adds power
>>3) More power equals lower clock
>
> #2 is clearly false.
>
> There are many cases where adding transistors
> results in lower power.

You aren't looking the context (which is in imaginary, theoretical everything else being equal land). I don't dispute what you are saying (above or below), you are obviously right. But you could add power saving transistors to an in-order design also. Going along that route we have already stepped out of simple.

> OOO can reduce power by making more efficient
> use of register file ports and alus, thus
> allowing the same performance at a lower,
> more power-efficient frequency.

Yes, but if out-of-order gives you zero performance benefit, it is quite hard to use it to save power.

>#1 is probably also false.
>
> Is identical performance the goal?

No. You can think that workload is such that out-of-order doesn't give you performance benefit or if it does, it is ignored. This really isn't about practical issues.

>#3 is probably also false.
>
> There may be other limitations to clock frequency
> such that power is not the critical factor.

Yes. I don't actually think it matters for my argument wether the relations are greater-than or greater-than-or-equal. The assumption about power is that there's no flexibility in power budget. The out-of-order design may not use a nanowatt more, even if it was ten times faster.

The whole point was about keeping everything else as equal as possible, just adding out-of-order capability.

If you want to know why I think this sort of non-practical discussion is beneficial at all, it is because I think it is important, or at least useful, to understand that deciding between OoO and IO is about compromizes and one compromize is that everything else being equal, out-of-order core uses more power, so it better offer something in exchange, e.g. even more performance.

The effect on clockspeed is really like an afterthought. Everything else being equal that's the only place to go for power save.

In real world you just don't take in-order core and add some out-of-order to it. You design the core with the knowledge that it will have OoO capabilities. I do believe that for most general purpose loads going for an OoO design is a right decision, so that isn't an issue.

There have been mentions of Computer Architecture: A Quantitative Approach by Hennessy and Patterson. They have also written a book Computer organization and design: the hardware/software interface. It has an infobox, about half a page in size which states among other things that pipelining has cost in complexity and power.

Should that be interpreted so that if you want to build a low power processor, don't use pipelining? Years ago maybe, but nowadays I'm not sure how much power you could save by using non-pipelined design and where would that saved power be useful (there are non-pipelined designs in use, but the reasons are probably mostly economical).

Still, the statement as such is probably true and for whatever reason, Hennessy and Patterson felt that they should include it in an introductory text book.

Now, I hope I made my (latest) point clear. It takes me nearly two hours on average to respond to AM's messages, this one took just about an hour. Nevertheless I don't really have time and resources discuss with multiple people at a time :) .

-JLarja