Jouni Osmala (josmala@cc.hut.fi) on 9/24/09 wrote:
---------------------------
>The original claim was never about clockrate it was all about IF-EX distance which
>you seemed total misunderstanding about.
>
>Lets put imaginary example with totally imaginary numbers to show what original meaning was.
>
>If inorder design takes 400 from IF-To EX and OoO takes 600.
>You can either
>A) clock lower the OoO.
>(the time required from if to ex is longer so OoO design would have 400/600 clockspeed.)
>
>B) Add extra stage to OoO to get it clock equally.
>( You divide the latency to more stages. so each stage requires less time than the original OoO design)
>
>C) Improve latch&clock design etc electrical design issues to reduce the latency
>of OoO design while keeping same number of stages.
>But you could do same for inorder design and then inorder design would clock higher if you didn't do B also.

From real designs it doesn't look like even the logical elongation of the pipeline is bound to be as large as you seem to think. Certainly not bound to be 2 stages as you asserted -- if that were really true, let me ask you how many stages would be left b/w IF and EX in MIPS R10K? Zero? And what about those with 1 stage like 603? :)

Or if applied to EV6, then a 6-issue in-order chip would end up 1 stage shorter than 4-issue EV5? Simply amazing. :)

If you really know how to do that, Jouni, I think you should circulate your CV to IBM, AMD, Intel etc. and enojoy the choosing process. And when you retire, you should write your own comp.arch book and explain how you were able to achieve that in your designs. :)

>And the only OoO design (EV6) that I thought did C. Did add a stage to pipeline also, AND clocked a tiny bit slower.

There's very little reason to presume that 575-612 MHz difference is entirely due to OoO; explanation could be as simple as the product of multiplier and bus speed used in respective motherboards. At least the highest speed on 0.35um is 600 MHz for both in my copies of hrms.

As for the extra stage in EV6, the 3 stages b/w IF and EX clearly identified are map, issue, and RF read. Stage after fetch simply shows nothing. So what exactly does it do?

>And H&P is the book you need to read to start understanding if you need any low
>level details. However H&P 3rd edition has OoO design included in it, and simply
>adds more stages to pipeline when adding OoO funcionality, I've quickly looked the
>3rd edition after recommending the reading H&P.

I recall you said OoOE adds two extra stages (another amazing discovery from you), and it's quite hard for me to believe that a reputable text could state something like that.

H&P is available on books.google.com, so why don't you refer to the page where they say something like this?

>>>> You're kidding, right?
>>>
>>>Sure. And your kidding with your black-and-white praise of out-of-order, right?
>>
>>What *exactly* of what I said do you consider a "black-and-white praise of out-of-order"?
>>Please, don't be shy to point it out for me and those who follow the thread.
>>
>>>> The only example he came up with to defend the
>>>> point is EV5, and, oh, looks like even in his
>>>> only example the time b/w IF and EX turns out
>>>> to be...
>>>
>>>Did you actually manage to come to an understanding on number of pipeline stages in those designs? :)
>>
>>What about him and you?
>
>IF in 603 does all the functions of the second stage of EV5 pipeline which simply
>makes your method of counting stages apples to oranges since you ignored stage 2
>of EV5 from counting the time in 603.

Actually, I use exactly your own metric here (the time b/w IF and EX stages), and you're still complaining?

Also the clockspeed for 603 in my comparison
>was before project "stretch" which increased its clockspeed by 50% without changing
>process and changed the name of chip. Do you have any proof that 603ev didn't change
>the number of pipeline stages from 603? Quick googling didn't show any mentions about number of stages it has.
>Other IBM project code named "stretch" was about adding pipeline stages.

No, I don't have proof that it kept pipeline the same. But I gather you don't have any counter-proof either. I think it's more likely that 603ev didn't add extra stages.

Actually, do you admit -- for a moment -- that some of your beliefs and ways you're used to thinking about CPUs might be wrong? Yes, simple as that? That higher clock in 603ev doesn't have to mean longer pipeline (could be other improvements that have absolutely nothing to do with pipeline length), or that OoOE in general doesn't necessarily mean lower clock or 2 extra stages b/w IF and EX, etc.?