Typical gate/transistor count for 32 bit FPU (NT)

By: Paul DeMone (pdemone.delete@this.igs.net), July 30, 2002 1:05 pm
Room: Moderated Discussions
Martin Høyer Kristiansen (mhkristiansen@yahoo.dk) on 7/30/02 wrote:
>Paul DeMone (pdemone@igs.net) on 7/26/02 wrote:
>>Martin Høyer Kristiansen (mhkristiansen@yahoo.dk) on 7/26/02 wrote:
>>>Out of curiosity.
>>>How many transistors does it typically take to implement a 32 bit FPU that can
>>>sustain 1 FMAC/cycle at say.. >1GHz in 0.13um ?
>>Including an approximation unit for division and square root but not a register
>>file, probably 1/3 to 1/2 million transistors. In terms of area, perhaps 1.5 to 2.0
>>mm2 in 0.13 um.
>The context I was pondering was the new line of graphics processors coming out
>from ATI (r300) and nVidia (nv30). They both deploy floating point pixel data types,
>and I was wondering just how much logic is consumed by a pixel processor (4 floating point units for RGBA).
>The new ATI part has 8 parallel pipes. It must be absolutely huge.

The FPU figures were for a fully IEEE compliant design.

Keep in mind that with a GPU you don't need much IEEE compliance and that can make a
huge difference. You don't need to worry about second order IEEE stuff like denorms,
NANs, modes, and exception handling. And you could even fudge the low order bits as
long as it doesn't affect image quality. Also operation latency isn't a big issue in a GPU
so you could be much less aggressive with parallelism in the multipliers to save logic.
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TopicPosted ByDate
Typical gate/transistor count for 32 bit FPU (NT)Martin Høyer Kristiansen2002/07/26 11:10 AM
  Damn, hit the NT button in the post above. (NT) (NT)Martin Høyer Kristiansen2002/07/26 11:11 AM
  Typical gate/transistor count for 32 bit FPU (NT)Paul DeMone2002/07/26 04:02 PM
    Typical gate/transistor count for 32 bit FPU (NT)Martin Høyer Kristiansen2002/07/30 10:39 AM
      Typical gate/transistor count for 32 bit FPU (NT)Paul DeMone2002/07/30 01:05 PM
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