Ok, I'm looking at the presentation here and it clearly states some things about the OOO core:


"Introduces out-of-order instruction issue and completion"
Ooo completion?


"Register renaming to enable execution speculation"
Good.


"Fast loop mode in instruction pre-fetch to lower power consumption"
Sounds a bit like nehalem's loop cache.


"Superscalar, dynamic multi-issue technology, on an efficient 8-stage pipeline"
Ok, so 8 stages.


"Continous fetch & decoding of 2 instructions per clock cycle"
Pretty straightforward - width of 2.


"Common instructions take 9 cycles, while complex instructions take up to 11 cycles"
This contradicts the 8 stages claim above, doesn't it?


"Out-of-order (OoO) instruction dispatch and completion Leverages OoO without traditional power/resource hungry reorder buffers"
Ok, this one has me really worried. No ROB? Are they half-assing something, or is there some new ROB-alternative that gives them "out of order completion" ?


"Supports dispatch of 4 instructions and completion of 7 instruction per clock cycle"
Right. But it only fetches 2. And they talk of dispatch width, not issue width. Are they using the terms interchangeably, or are they hiding something?
The diagram shows what looks like it could be either a 3-port or 4-port scheduler. Are "FPU/NEON" and "address" sent to a single port?