By: anon (no.delete@this.thanks.com), September 16, 2009 8:58 pm
Room: Moderated Discussions
someone (someone@somewhere.com) on 9/16/09 wrote:
---------------------------
>Seni (seniike@hotmail.com) on 9/16/09 wrote:
>---------------------------
>
>>
>>"Common instructions take 9 cycles, while complex instructions take up to 11 cycles"
>>This contradicts the 8 stages claim above, doesn't it?
>>
>
>The 8 stage pipeline is almost certainly the mispredict
>pipeline. Basic instructions likely have one more stage
>for writeback and/or retire.
>
>>
>>"Out-of-order (OoO) instruction dispatch and completion Leverages OoO without traditional
>>power/resource hungry reorder buffers"
>>Ok, this one has me really worried. No ROB? Are they half-assing something, or
>>is there some new ROB-alternative that gives them "out of order completion" ?
>
>How about an *old* ROB alternative - rename registers
>like the EV6.
Hmm. In retrospect the OoO mechanism of the 21246 is too centralized. Whereas with the ROB and other structures the OoO hardware is more distributed, to take advantages of the mismatch of wires and transistor speeds in sub 100 nm process features sizes.
---------------------------
>Seni (seniike@hotmail.com) on 9/16/09 wrote:
>---------------------------
>
>>
>>"Common instructions take 9 cycles, while complex instructions take up to 11 cycles"
>>This contradicts the 8 stages claim above, doesn't it?
>>
>
>The 8 stage pipeline is almost certainly the mispredict
>pipeline. Basic instructions likely have one more stage
>for writeback and/or retire.
>
>>
>>"Out-of-order (OoO) instruction dispatch and completion Leverages OoO without traditional
>>power/resource hungry reorder buffers"
>>Ok, this one has me really worried. No ROB? Are they half-assing something, or
>>is there some new ROB-alternative that gives them "out of order completion" ?
>
>How about an *old* ROB alternative - rename registers
>like the EV6.
Hmm. In retrospect the OoO mechanism of the 21246 is too centralized. Whereas with the ROB and other structures the OoO hardware is more distributed, to take advantages of the mismatch of wires and transistor speeds in sub 100 nm process features sizes.
Topic | Posted By | Date |
---|---|---|
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ARM announces 2GHz netbook CPU | Potatoswatter | 2009/09/16 04:12 PM |
ARM announces 2GHz netbook CPU | Megol | 2009/09/16 04:21 PM |
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ARM announces 2GHz netbook CPU | Megol | 2009/09/18 11:54 AM |
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ARM announces 2GHz netbook CPU | Seni | 2009/09/16 06:41 PM |
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ARM announces 2GHz netbook CPU | anon | 2009/09/16 08:58 PM |
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ARM announces 2GHz netbook CPU | someone | 2009/09/17 06:10 AM |
ARM announces 2GHz netbook CPU | David Kanter | 2009/09/17 03:02 PM |
ARM announces 2GHz netbook CPU | anon | 2009/09/20 05:34 PM |
ARM announces 2GHz netbook CPU | Seni | 2009/09/17 02:05 PM |
ARM announces 2GHz netbook CPU | Wilco | 2009/09/17 03:29 PM |
ARM announces 2GHz netbook CPU | Seni | 2009/09/17 03:53 PM |
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ARM announces 2GHz netbook CPU | David Kanter | 2009/09/18 04:17 PM |
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ARM announces 2GHz netbook CPU | Wilco | 2009/09/18 01:56 AM |
ARM announces 2GHz netbook CPU | Jouni Osmala | 2009/09/18 04:46 AM |
ARM announces 2GHz netbook CPU | Michael S | 2009/09/18 06:22 AM |
ARM announces 2GHz netbook CPU | Wilco | 2009/09/18 11:36 AM |
ARM announces 2GHz netbook CPU | rcf | 2009/09/19 08:49 AM |
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ARM announces 2GHz netbook CPU | AM | 2009/09/19 03:41 AM |
ARM announces 2GHz netbook CPU | Michael S | 2009/09/18 05:15 AM |
ARM announces 2GHz netbook CPU | Michael S | 2009/09/18 05:48 AM |
ARM announces 2GHz netbook CPU | Wilco | 2009/09/18 01:15 PM |
ARM announces 2GHz netbook CPU | Michael S | 2009/09/20 09:00 AM |
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ARM announces 2GHz netbook CPU | Michael S | 2009/09/20 10:42 AM |
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ARM announces 2GHz netbook CPU | Wilco | 2009/09/21 03:38 AM |
ARM announces 2GHz netbook CPU | Linus Torvalds | 2009/09/21 07:05 AM |
ARM announces 2GHz netbook CPU | none | 2009/09/21 07:10 AM |
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